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git01.mediatek.com / filogic / uboot / 0cbc4cb6e3c731e88577f426302a3e41217a5a9d / arch / arm / cpu / armv7 / sunxi / dram_sun4i.c
  1. ad0dfc5 sun4i: Rename dram_clk_cfg to dram_clk_gate by Hans de Goede · Sun Nov 09 12:24:55 2014 +0100
  2. 5037c45 sun4i: Rename dram files to dram_sun4i.x by Hans de Goede · Sun Nov 02 20:31:16 2014 +0100[Renamed from arch/arm/cpu/armv7/sunxi/dram.c]
  3. 8f32aaa sunxi: Use CONFIG_MACH_SUN?I from Kconfig instead of CONFIG_SUN?I by Ian Campbell · Fri Oct 24 21:20:47 2014 +0100
  4. 05e5bcb sunxi: Add CONFIG_OLD_SUNXI_KERNEL_COMPAT Kconfig option by Hans de Goede · Wed Oct 22 14:56:36 2014 +0200
  5. 1c21155 sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcoding by Hans de Goede · Wed Oct 22 14:48:38 2014 +0200
  6. ea7cdd1 sunxi: dram: Autodetect DDR3 bus width and density by Siarhei Siamashka · Sun Aug 03 05:32:54 2014 +0300
  7. ac7b6fc sunxi: dram: Derive write recovery delay from DRAM clock speed by Siarhei Siamashka · Sun Aug 03 05:32:53 2014 +0300
  8. b41aa97 sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory by Siarhei Siamashka · Sun Aug 03 05:32:52 2014 +0300
  9. b1ace77 sunxi: dram: Configurable DQS gating window mode and delay by Siarhei Siamashka · Sun Aug 03 05:32:51 2014 +0300
  10. c4f0aa5 sunxi: dram: Add a helper function 'mctl_get_number_of_lanes' by Siarhei Siamashka · Sun Aug 03 05:32:50 2014 +0300
  11. 8e9c4fd sunxi: dram: Improve DQS gate data training error handling by Siarhei Siamashka · Sun Aug 03 05:32:49 2014 +0300
  12. 020a634 sunxi: dram: Use divisor P=1 for PLL5 by Siarhei Siamashka · Sun Aug 03 05:32:48 2014 +0300
  13. 586757a sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6) by Siarhei Siamashka · Sun Aug 03 05:32:47 2014 +0300
  14. 3ad063a sunxi: dram: Re-introduce the impedance calibration ond ODT by Siarhei Siamashka · Sun Aug 03 05:32:46 2014 +0300
  15. 72ed869 sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions by Siarhei Siamashka · Sun Aug 03 05:32:45 2014 +0300
  16. d89297a sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i by Siarhei Siamashka · Sun Aug 03 05:32:44 2014 +0300
  17. 6f66418 sunxi: dram: Remove broken impedance and ODT configuration code by Siarhei Siamashka · Sun Aug 03 05:32:43 2014 +0300
  18. ce4d21c sunxi: dram: Fix CKE delay handling for sun4i/sun5i by Siarhei Siamashka · Sun Aug 03 05:32:42 2014 +0300
  19. a1d9f03 sunxi: dram: Respect the DDR3 reset timing requirements by Siarhei Siamashka · Sun Aug 03 05:32:41 2014 +0300
  20. 551bfb9 sunxi: dram: Remove broken super-standby remnants by Siarhei Siamashka · Sun Aug 03 05:32:40 2014 +0300
  21. 27942f1 sunxi: dram: Remove useless 'dramc_scan_dll_para()' function by Siarhei Siamashka · Sun Aug 03 05:32:39 2014 +0300
  22. 8c1c782 sunxi: Add sun5i support by Hans de Goede · Mon Jun 09 11:36:58 2014 +0200
  23. 3ab9c23 sunxi: Add sun4i support by Hans de Goede · Mon Jun 09 11:36:57 2014 +0200
  24. 2f1afcc sunxi: add sun7i dram setup support by Ian Campbell · Mon May 05 11:52:25 2014 +0100