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git01.mediatek.com / filogic / uboot / 0ab8678613ec95e1104a8aa92ba9f3afa5067c1e / arch / riscv / cpu / generic / Kconfig
  1. 026a932 riscv: define a cache line size for the generic CPU by Heinrich Schuchardt · Fri Jul 21 18:01:18 2023 +0200
  2. b5f0372 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · Wed Jun 21 23:11:46 2023 +0800
  3. 1255ab8 riscv: qemu: Switch to use binman to generate u-boot.itb by Bin Meng · Mon May 10 20:23:39 2021 +0800
  4. 614b1d8 riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · Tue May 11 20:04:12 2021 +0800
  5. 2f00216 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · Mon Mar 15 18:11:18 2021 +1300
  6. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  7. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  8. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  9. 1240cd6 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · Mon Feb 25 08:14:10 2019 +0000[Renamed (91%) from arch/riscv/cpu/qemu/Kconfig]
  10. 16c80d7 Merge tag 'efi-2019-04-rc3' of https://github.com/xypron2/u-boot by Tom Rini · Tue Feb 26 08:45:08 2019 -0500