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git01.mediatek.com / filogic / uboot / 0ab8678613ec95e1104a8aa92ba9f3afa5067c1e / arch / riscv / cpu / fu740
  1. 2e71a9e board: sifive: Rename spl_soc_init() to spl_dram_init() by Lukas Funke · Wed Apr 24 09:43:38 2024 +0200
  2. b6b9900 riscv: Remove common.h usage by Tom Rini · Thu Oct 12 19:03:59 2023 -0400
  3. 51a9aac common: return type board_get_usable_ram_top by Heinrich Schuchardt · Sat Aug 12 20:16:58 2023 +0200
  4. b5f0372 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · Wed Jun 21 23:11:46 2023 +0800
  5. 4f4f583 board_f: Fix types for board_get_usable_ram_top() by Pali Rohár · Fri Sep 09 17:32:40 2022 +0200
  6. 9b9c4d5 riscv: Enable SPI flash env for SiFive Unmatched. by Thomas Skibo · Wed Nov 24 14:32:10 2021 -0800
  7. ec34849 board: sifive: use ccache driver instead of helper function by Zong Li · Wed Sep 01 15:01:42 2021 +0800
  8. f1ac8fa riscv: cpu: fu740: Fix typo of date by Zong Li · Mon Aug 02 15:34:14 2021 +0800
  9. bccfc2e i2c: Rename SPL/TPL_I2C_SUPPORT to I2C by Simon Glass · Sat Jul 10 21:14:36 2021 -0600
  10. 9627a8e riscv: sifive: fu740: Support i2c in spl by Zong Li · Wed Jun 30 23:23:47 2021 +0800
  11. 3376055 riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller by Zong Li · Wed Jun 30 23:23:46 2021 +0800
  12. 26190b8 riscv: cpu: fu740: clear feature disable CSR by Green Wan · Thu May 27 06:52:14 2021 -0700
  13. 7f33743 riscv: cpu: fu740: Add support for cpu fu740 by Green Wan · Thu May 27 06:52:07 2021 -0700