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git01.mediatek.com / filogic / uboot / 068962bb3675085aa4316d0b9a9b2f77424d9e70 / arch / arm / mach-sunxi / dram_sunxi_dw.c
  1. 16f6f79 sunxi: dram: make MBUS configuration functions static by Andre Przywara · Wed Jun 07 01:07:41 2023 +0100
  2. bb4dd96 global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* by Tom Rini · Wed Nov 16 13:10:37 2022 -0500
  3. c3391f6 sunxi: enable dual rank memory on R40 by Icenowy Zheng · Fri Feb 26 00:13:25 2021 +0800
  4. 9e9b073 sunxi: support asymmetric dual rank DRAM on A64/R40 by Icenowy Zheng · Fri Feb 26 00:13:24 2021 +0800
  5. aff2d3a sunxi: make V3s DRAM initialization more proper by Icenowy Zheng · Fri Oct 16 17:33:08 2020 +0800
  6. a1dba89 sunxi: Silence warning about non-static inline function by Samuel Holland · Thu May 07 18:02:33 2020 -0500
  7. dbd7954 common: Drop linux/delay.h from common header by Simon Glass · Sun May 10 11:40:11 2020 -0600
  8. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  9. 9758973 common: Drop init.h from common header by Simon Glass · Sun May 10 11:40:02 2020 -0600
  10. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  11. 3c1b9f1 sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller by Icenowy Zheng · Sat Jun 03 17:10:23 2017 +0800
  12. fe05217 sunxi: add support for V3s DRAM controller by Icenowy Zheng · Sat Jun 03 17:10:21 2017 +0800
  13. e270a58 sunxi: add support for the DDR2 in V3s SoC by Icenowy Zheng · Sat Jun 03 17:10:20 2017 +0800
  14. 8804877 sunxi: enable dual rank detection in DesignWare-like DRAM code by Icenowy Zheng · Sat Jun 03 17:10:19 2017 +0800
  15. f09b48e sunxi: Add selective DRAM type and timing by Icenowy Zheng · Sat Jun 03 17:10:18 2017 +0800
  16. 2002035 sunxi: add bank detection code to H3 DRAM initialization code by Icenowy Zheng · Sat Jun 03 17:10:17 2017 +0800
  17. b260751 sunxi: add option for 16-bit DW DRAM controller by Icenowy Zheng · Sat Jun 03 17:10:16 2017 +0800
  18. 4323a8f sunxi: Rename bus-width related macros in H3 DRAM code by Icenowy Zheng · Sat Jun 03 17:10:15 2017 +0800
  19. ca0bc02 sunxi: makes an invisible option for H3-like DRAM controllers by Icenowy Zheng · Sat Jun 03 17:10:14 2017 +0800[Renamed from arch/arm/mach-sunxi/dram_sun8i_h3.c]
  20. 143ef79 sunxi: Use H3/A64 DRAM initialization code for R40 by Chen-Yu Tsai · Thu Dec 01 19:09:57 2016 +0800
  21. 5d0d28f sunxi: DRAM: add Allwinner H5 support by Andre Przywara · Thu Feb 16 01:20:26 2017 +0000
  22. d414c38 sunxi: DRAM: fix H3 DRAM size display on aarch64 by Andre Przywara · Mon Jan 02 11:48:44 2017 +0000
  23. c98f5cc sunxi: H3/A64: fix non-ODT setting by Andre Przywara · Mon Jan 02 11:48:43 2017 +0000
  24. f613817 sunxi: A64: use H3 DRAM initialization code for A64 as well by Jens Kuske · Mon Jan 02 11:48:42 2017 +0000
  25. 8bbadc8 sunxi: H3: add DRAM controller single bit delay support by Jens Kuske · Mon Jan 02 11:48:40 2017 +0000
  26. 3e79758 sunxi: H3: add and rename some DRAM contoller registers by Jens Kuske · Mon Jan 02 11:48:39 2017 +0000
  27. 3c31ba9 sunxi: H3: Rework MBUS priority setup by Philipp Tomsich · Mon Jan 02 11:48:38 2017 +0000
  28. d8b9593 sunxi: Fix H3 DRAM impedance calibration on rev. A chips by Jens Kuske · Wed Sep 21 20:08:30 2016 +0200
  29. 8dd84a7 sunxi: Move cpu independent code to mach directory by Alexander Graf · Tue Mar 29 17:29:06 2016 +0200[Renamed from arch/arm/cpu/armv7/sunxi/dram_sun8i_h3.c]
  30. af272a1 sunxi: Fix H3 DRAM DQ read delay configuration by Jens Kuske · Thu Dec 10 11:41:02 2015 +0100
  31. 53f018e sunxi: Add H3 DRAM initialization support by Jens Kuske · Tue Nov 17 15:12:59 2015 +0100