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git01.mediatek.com / filogic / uboot / 0357a76e199e70141dd2246fe0e0c47bbcc86ea3 / arch / powerpc / cpu / mpc8xxx / ddr / ddr.h
  1. e73cc04 powerpc/mpc8xxx: Enable calculation for fixed DDR chips by York Sun · Tue Jun 07 09:42:16 2011 +0800
  2. b78c7bf powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() by Kumar Gala · Mon Jan 31 20:36:02 2011 -0600
  3. 27f83be powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 by York Sun · Thu Feb 10 10:13:10 2011 -0800
  4. 80ad401 8xxx/ddr: add support to only compute the ddr sdram size by Haiying Wang · Wed Dec 01 10:35:31 2010 -0500
  5. 93799ca powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 by york · Fri Jul 02 22:25:52 2010 +0000
  6. 88fbf93 Move arch/ppc to arch/powerpc by Stefan Roese · Thu Apr 15 16:07:28 2010 +0200[Renamed from arch/ppc/cpu/mpc8xxx/ddr/ddr.h]
  7. 29514c7 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU by Peter Tyser · Mon Apr 12 22:28:09 2010 -0500[Renamed from cpu/mpc8xxx/ddr/ddr.h]
  8. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  9. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  10. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
  11. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500