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git01.mediatek.com / filogic / uboot / fff928ca15a50d9f6ef097c2283d390d622140ed / . / arch / powerpc / dts / t4240rdb.dts
blob: c33b4982ba329061fb8202e179f49e3fd84be9fc [file] [log] [blame]
Hou Zhiqiang245d4922019-08-20 09:35:25 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * T4240RDB Device Tree Source
4 *
5 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
Camelia Groza9ebd56f2023-07-11 15:49:21 +0300[diff] [blame]6 * Copyright 2019-2023 NXP
Hou Zhiqiang245d4922019-08-20 09:35:25 +0000[diff] [blame]7 */
8
9/include/ "t4240.dtsi"
10
11/ {
12 model = "fsl,T4240RDB";
13 compatible = "fsl,T4240RDB";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&mpic>;
Xiaowei Bao78860bd2020-06-04 23:17:01 +0800[diff] [blame]17
18 aliases {
19 spi0 = &espi0;
Camelia Groza9ebd56f2023-07-11 15:49:21 +0300[diff] [blame]20 serial0 = &serial0;
21 serial1 = &serial1;
22 serial2 = &serial2;
23 serial3 = &serial3;
Xiaowei Bao78860bd2020-06-04 23:17:01 +0800[diff] [blame]24 };
25};
26
Camelia Groza028d0572021-04-13 19:48:00 +0300[diff] [blame]27&soc {
28 fman@400000 {
29 ethernet@e0000 {
30 phy-handle = <&sgmiiphy21>;
31 phy-connection-type = "sgmii";
32 };
33
34 ethernet@e2000 {
35 phy-handle = <&sgmiiphy22>;
36 phy-connection-type = "sgmii";
37 };
38
39 ethernet@e4000 {
40 phy-handle = <&sgmiiphy23>;
41 phy-connection-type = "sgmii";
42 };
43
44 ethernet@e6000 {
45 phy-handle = <&sgmiiphy24>;
46 phy-connection-type = "sgmii";
47 };
48
49 ethernet@e8000 {
50 status = "disabled";
51 };
52
53 ethernet@ea000 {
54 status = "disabled";
55 };
56
57 ethernet@f0000 {
58 phy-handle = <&xfiphy1>;
59 phy-connection-type = "xgmii";
60 };
61
62 ethernet@f2000 {
63 phy-handle = <&xfiphy2>;
64 phy-connection-type = "xgmii";
65 };
66 };
67
68 fman@500000 {
69 ethernet@e0000 {
70 phy-handle = <&sgmiiphy41>;
71 phy-connection-type = "sgmii";
72 };
73
74 ethernet@e2000 {
75 phy-handle = <&sgmiiphy42>;
76 phy-connection-type = "sgmii";
77 };
78
79 ethernet@e4000 {
80 phy-handle = <&sgmiiphy43>;
81 phy-connection-type = "sgmii";
82 };
83
84 ethernet@e6000 {
85 phy-handle = <&sgmiiphy44>;
86 phy-connection-type = "sgmii";
87 };
88
89 ethernet@e8000 {
90 status = "disabled";
91 };
92
93 ethernet@ea000 {
94 status = "disabled";
95 };
96
97 ethernet@f0000 {
98 phy-handle = <&xfiphy3>;
99 phy-connection-type = "xgmii";
100 };
101
102 ethernet@f2000 {
103 phy-handle = <&xfiphy4>;
104 phy-connection-type = "xgmii";
105 };
106
Camelia Groza7b9b65d2021-04-13 19:48:01 +0300[diff] [blame]107 mdio@5fc000 {
Camelia Groza028d0572021-04-13 19:48:00 +0300[diff] [blame]108 sgmiiphy21: ethernet-phy@0 {
109 reg = <0x0>;
110 };
111
112 sgmiiphy22: ethernet-phy@1 {
113 reg = <0x1>;
114 };
115
116 sgmiiphy23: ethernet-phy@2 {
117 reg = <0x2>;
118 };
119
120 sgmiiphy24: ethernet-phy@3 {
121 reg = <0x3>;
122 };
123
124 sgmiiphy41: ethernet-phy@4 {
125 reg = <0x4>;
126 };
127
128 sgmiiphy42: ethernet-phy@5 {
129 reg = <0x5>;
130 };
131
132 sgmiiphy43: ethernet-phy@6 {
133 reg = <0x6>;
134 };
135
136 sgmiiphy44: ethernet-phy@7 {
137 reg = <0x7>;
138 };
139 };
140
Camelia Groza7b9b65d2021-04-13 19:48:01 +0300[diff] [blame]141 mdio@5fd000 {
Camelia Groza028d0572021-04-13 19:48:00 +0300[diff] [blame]142 xfiphy1: ethernet-phy@10 {
143 compatible = "ethernet-phy-id13e5.1002";
144 reg = <0x10>;
145 };
146
147 xfiphy2: ethernet-phy@11 {
148 compatible = "ethernet-phy-id13e5.1002";
149 reg = <0x11>;
150 };
151
152 xfiphy3: ethernet-phy@13 {
153 compatible = "ethernet-phy-id13e5.1002";
154 reg = <0x13>;
155 };
156
157 xfiphy4: ethernet-phy@12 {
158 compatible = "ethernet-phy-id13e5.1002";
159 reg = <0x12>;
160 };
161 };
162 };
163};
164
Xiaowei Bao78860bd2020-06-04 23:17:01 +0800[diff] [blame]165&espi0 {
166 status = "okay";
167 flash@0 {
168 compatible = "jedec,spi-nor";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 reg = <0>;
172 spi-max-frequency = <10000000>; /* input clock */
173 };
Hou Zhiqiang245d4922019-08-20 09:35:25 +0000[diff] [blame]174};
Camelia Groza028d0572021-04-13 19:48:00 +0300[diff] [blame]175
176/include/ "t4240si-post.dtsi"