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git01.mediatek.com / filogic / uboot / ffec940cb1a1639b5efe899e0fc3cc8ea0210a2a / . / drivers / clk / renesas / r9a07g044-cpg.c
blob: 2336028a736717577c0a3f67fbc14af3a643beaa [file] [log] [blame]
Paul Barker132d7ea2023-10-16 10:25:29 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * RZ/G2L CPG driver
4 *
5 * Copyright (C) 2021-2023 Renesas Electronics Corp.
6 */
7
8#include <common.h>
9#include <dm/device.h>
10#include <dt-bindings/clock/r9a07g044-cpg.h>
11#include <linux/clk-provider.h>
12
13#include "rzg2l-cpg.h"
14
15/* Divider tables */
16static const struct clk_div_table dtable_1_8[] = {
17 {0, 1},
18 {1, 2},
19 {2, 4},
20 {3, 8},
21 {0, 0},
22};
23
24static const struct clk_div_table dtable_1_32[] = {
25 {0, 1},
26 {1, 2},
27 {2, 4},
28 {3, 8},
29 {4, 32},
30 {0, 0},
31};
32
33static const struct clk_div_table dtable_16_128[] = {
34 {0, 16},
35 {1, 32},
36 {2, 64},
37 {3, 128},
38 {0, 0},
39};
40
41/* Mux clock tables */
42static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
43static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
44static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
45static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
46static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
47
48static const struct {
49 struct cpg_core_clk common[56];
50} core_clks = {
51 .common = {
52 /* External Clock Inputs */
53 DEF_INPUT("extal", CLK_EXTAL),
54
55 /* Internal Core Clocks */
56 DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
57 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
58 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
59 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
60 DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
61 DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
62 DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
63 DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
64
65 DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
66 DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
67
68 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
69
70 DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
71 DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
72 DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
73 DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
74 DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
75
76 DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
77 DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
78
79 DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2),
80
81 DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
82 DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
83 DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
84 DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
85 DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
86 DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
87
88 DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
89 DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
90 DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2),
91 DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),
92 DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
93 DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),
94 DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
95 DIVDSILPCLK, dtable_16_128),
96
97 /* Core output clk */
98 DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
99 DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
100 DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
101 DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
102 DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
103 DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
104 DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
105 DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
106 DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
107 DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
108 DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
109 DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
110 DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi),
111 DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi),
112 DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
113 DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
114 DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),
115 DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
116 DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
117 DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
118 DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
119 DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
120 DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1),
121 },
122};
123
124static const struct {
125 struct rzg2l_mod_clk common[79];
126} mod_clks = {
127 .common = {
128 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
129 0x514, 0),
130 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
131 0x518, 0),
132 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
133 0x518, 1),
134 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
135 0x52c, 0),
136 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
137 0x52c, 1),
138 DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
139 0x534, 0),
140 DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
141 0x534, 1),
142 DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
143 0x534, 2),
144 DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
145 0x538, 0),
146 DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
147 0x540, 0),
148 DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
149 0x544, 0),
150 DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
151 0x544, 1),
152 DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
153 0x544, 2),
154 DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
155 0x544, 3),
156 DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
157 0x548, 0),
158 DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
159 0x548, 1),
160 DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
161 0x548, 2),
162 DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
163 0x548, 3),
164 DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
165 0x550, 0),
166 DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
167 0x550, 1),
168 DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
169 0x554, 0),
170 DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
171 0x554, 1),
172 DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
173 0x554, 2),
174 DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
175 0x554, 3),
176 DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
177 0x554, 4),
178 DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
179 0x554, 5),
180 DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
181 0x554, 6),
182 DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
183 0x554, 7),
184 DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G,
185 0x558, 0),
186 DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
187 0x558, 1),
188 DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
189 0x558, 2),
190 DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
191 0x564, 0),
192 DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
193 0x564, 1),
194 DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
195 0x564, 2),
196 DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
197 0x564, 3),
198 DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
199 0x568, 0),
200 DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
201 0x568, 1),
202 DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
203 0x568, 2),
204 DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
205 0x568, 3),
206 DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
207 0x568, 4),
208 DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
209 0x568, 5),
210 DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
211 0x56c, 0),
212 DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
213 0x56c, 0),
214 DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
215 0x56c, 1),
216 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
217 0x570, 0),
218 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
219 0x570, 1),
220 DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
221 0x570, 2),
222 DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
223 0x570, 3),
224 DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
225 0x570, 4),
226 DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
227 0x570, 5),
228 DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
229 0x570, 6),
230 DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
231 0x570, 7),
232 DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
233 0x578, 0),
234 DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
235 0x578, 1),
236 DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
237 0x578, 2),
238 DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
239 0x578, 3),
240 DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
241 0x57c, 0),
242 DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
243 0x57c, 0),
244 DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
245 0x57c, 1),
246 DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
247 0x57c, 1),
248 DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
249 0x580, 0),
250 DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
251 0x580, 1),
252 DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
253 0x580, 2),
254 DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
255 0x580, 3),
256 DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
257 0x584, 0),
258 DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
259 0x584, 1),
260 DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
261 0x584, 2),
262 DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
263 0x584, 3),
264 DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
265 0x584, 4),
266 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
267 0x588, 0),
268 DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
269 0x588, 1),
270 DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
271 0x590, 0),
272 DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
273 0x590, 1),
274 DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
275 0x590, 2),
276 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
277 0x594, 0),
278 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
279 0x598, 0),
280 DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
281 0x5a8, 0),
282 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
283 0x5a8, 1),
284 DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
285 0x5ac, 0),
286 },
287};
288
289static const struct rzg2l_reset r9a07g044_resets[] = {
290 DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
291 DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
292 DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
293 DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
294 DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
295 DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
296 DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
297 DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
298 DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
299 DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
300 DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
301 DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
302 DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
303 DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
304 DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
305 DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
306 DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
307 DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
308 DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
309 DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
310 DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
311 DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
312 DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
313 DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
314 DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
315 DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
316 DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
317 DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
318 DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
319 DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
320 DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
321 DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
322 DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
323 DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
324 DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
325 DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
326 DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
327 DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
328 DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
329 DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
330 DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
331 DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
332 DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
333 DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
334 DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
335 DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
336 DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
337 DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
338 DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
339 DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
340 DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
341 DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
342 DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
343 DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
344 DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
345 DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
346 DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
347 DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
348 DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
349 DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
350 DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
351};
352
353const struct rzg2l_cpg_info r9a07g044_cpg_info = {
354 /* Core Clocks */
355 .core_clks = core_clks.common,
356 .num_core_clks = ARRAY_SIZE(core_clks.common),
357
358 /* Module Clocks */
359 .mod_clks = mod_clks.common,
360 .num_mod_clks = ARRAY_SIZE(mod_clks.common),
361 .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
362
363 /* Resets */
364 .resets = r9a07g044_resets,
365 .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
366
367 .has_clk_mon_regs = true,
368};
369
370static const struct udevice_id r9a07g044_cpg_ids[] = {
371 {
372 .compatible = "renesas,r9a07g044-cpg",
373 .data = (unsigned long)&r9a07g044_cpg_info,
374 },
375 { /* sentinel */ }
376};
377
378U_BOOT_DRIVER(r9a07g044_cpg) = {
379 .name = "r9a07g044-cpg",
380 .id = UCLASS_NOP,
381 .of_match = r9a07g044_cpg_ids,
382 .bind = rzg2l_cpg_bind,
383 .flags = DM_FLAG_PRE_RELOC,
384};