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git01.mediatek.com / filogic / uboot / ffa544238e620f5bdc1769793e9769b57a91129c / . / arch / x86 / dts / conga-qeval20-qa3-e3845.dts
blob: 1a4ecaad0e917d2ac3ec038f227a6cf282128e4a [file] [log] [blame]
Stefan Roese2a0b94c2016-03-16 08:48:21 +0100[diff] [blame]1/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/dts-v1/;
9
10#include <dt-bindings/gpio/x86-gpio.h>
11#include <dt-bindings/interrupt-router/intel-irq.h>
12
13/include/ "skeleton.dtsi"
14/include/ "serial.dtsi"
15/include/ "rtc.dtsi"
16/include/ "tsc_timer.dtsi"
17
18/ {
19 model = "congatec-QEVAL20-QA3-E3845";
20 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
21
22 aliases {
23 serial0 = &serial;
24 spi0 = &spi;
25 };
26
27 config {
28 silent_console = <0>;
29 };
30
31 pch_pinctrl {
32 compatible = "intel,x86-pinctrl";
33 };
34
35 chosen {
36 stdout-path = "/serial";
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu@0 {
44 device_type = "cpu";
45 compatible = "intel,baytrail-cpu";
46 reg = <0>;
47 intel,apic-id = <0>;
48 };
49
50 cpu@1 {
51 device_type = "cpu";
52 compatible = "intel,baytrail-cpu";
53 reg = <1>;
54 intel,apic-id = <2>;
55 };
56
57 cpu@2 {
58 device_type = "cpu";
59 compatible = "intel,baytrail-cpu";
60 reg = <2>;
61 intel,apic-id = <4>;
62 };
63
64 cpu@3 {
65 device_type = "cpu";
66 compatible = "intel,baytrail-cpu";
67 reg = <3>;
68 intel,apic-id = <6>;
69 };
70 };
71
72 pci {
73 compatible = "intel,pci-baytrail", "pci-x86";
74 #address-cells = <3>;
75 #size-cells = <2>;
76 u-boot,dm-pre-reloc;
77 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
78 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
79 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
80
81 pch@1f,0 {
82 reg = <0x0000f800 0 0 0 0>;
83 compatible = "pci8086,0f1c", "intel,pch9";
84 #address-cells = <1>;
85 #size-cells = <1>;
86
87 irq-router {
88 compatible = "intel,irq-router";
89 intel,pirq-config = "ibase";
90 intel,ibase-offset = <0x50>;
Bin Meng0651f622016-05-07 07:46:15 -0700[diff] [blame]91 intel,actl-addr = <0>;
Stefan Roese2a0b94c2016-03-16 08:48:21 +0100[diff] [blame]92 intel,pirq-link = <8 8>;
93 intel,pirq-mask = <0xdee0>;
94 intel,pirq-routing = <
95 /* BayTrail PCI devices */
96 PCI_BDF(0, 2, 0) INTA PIRQA
97 PCI_BDF(0, 3, 0) INTA PIRQA
98 PCI_BDF(0, 16, 0) INTA PIRQA
99 PCI_BDF(0, 17, 0) INTA PIRQA
100 PCI_BDF(0, 18, 0) INTA PIRQA
101 PCI_BDF(0, 19, 0) INTA PIRQA
102 PCI_BDF(0, 20, 0) INTA PIRQA
103 PCI_BDF(0, 21, 0) INTA PIRQA
104 PCI_BDF(0, 22, 0) INTA PIRQA
105 PCI_BDF(0, 23, 0) INTA PIRQA
106 PCI_BDF(0, 24, 0) INTA PIRQA
107 PCI_BDF(0, 24, 1) INTC PIRQC
108 PCI_BDF(0, 24, 2) INTD PIRQD
109 PCI_BDF(0, 24, 3) INTB PIRQB
110 PCI_BDF(0, 24, 4) INTA PIRQA
111 PCI_BDF(0, 24, 5) INTC PIRQC
112 PCI_BDF(0, 24, 6) INTD PIRQD
113 PCI_BDF(0, 24, 7) INTB PIRQB
114 PCI_BDF(0, 26, 0) INTA PIRQA
115 PCI_BDF(0, 27, 0) INTA PIRQA
116 PCI_BDF(0, 28, 0) INTA PIRQA
117 PCI_BDF(0, 28, 1) INTB PIRQB
118 PCI_BDF(0, 28, 2) INTC PIRQC
119 PCI_BDF(0, 28, 3) INTD PIRQD
120 PCI_BDF(0, 29, 0) INTA PIRQA
121 PCI_BDF(0, 30, 0) INTA PIRQA
122 PCI_BDF(0, 30, 1) INTD PIRQD
123 PCI_BDF(0, 30, 2) INTB PIRQB
124 PCI_BDF(0, 30, 3) INTC PIRQC
125 PCI_BDF(0, 30, 4) INTD PIRQD
126 PCI_BDF(0, 30, 5) INTB PIRQB
127 PCI_BDF(0, 31, 3) INTB PIRQB
128
129 /*
130 * PCIe root ports downstream
131 * interrupts
132 */
133 PCI_BDF(1, 0, 0) INTA PIRQA
134 PCI_BDF(1, 0, 0) INTB PIRQB
135 PCI_BDF(1, 0, 0) INTC PIRQC
136 PCI_BDF(1, 0, 0) INTD PIRQD
137 PCI_BDF(2, 0, 0) INTA PIRQB
138 PCI_BDF(2, 0, 0) INTB PIRQC
139 PCI_BDF(2, 0, 0) INTC PIRQD
140 PCI_BDF(2, 0, 0) INTD PIRQA
141 PCI_BDF(3, 0, 0) INTA PIRQC
142 PCI_BDF(3, 0, 0) INTB PIRQD
143 PCI_BDF(3, 0, 0) INTC PIRQA
144 PCI_BDF(3, 0, 0) INTD PIRQB
145 PCI_BDF(4, 0, 0) INTA PIRQD
146 PCI_BDF(4, 0, 0) INTB PIRQA
147 PCI_BDF(4, 0, 0) INTC PIRQB
148 PCI_BDF(4, 0, 0) INTD PIRQC
149 >;
150 };
151
152 spi: spi {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "intel,ich9-spi";
156 spi-flash@0 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 reg = <0>;
160 compatible = "stmicro,n25q064a",
161 "spi-flash";
162 memory-map = <0xff800000 0x00800000>;
163 rw-mrc-cache {
164 label = "rw-mrc-cache";
165 reg = <0x006f0000 0x00010000>;
166 };
167 };
168 };
169
170 gpioa {
171 compatible = "intel,ich6-gpio";
172 u-boot,dm-pre-reloc;
173 reg = <0 0x20>;
174 bank-name = "A";
175 };
176
177 gpiob {
178 compatible = "intel,ich6-gpio";
179 u-boot,dm-pre-reloc;
180 reg = <0x20 0x20>;
181 bank-name = "B";
182 };
183
184 gpioc {
185 compatible = "intel,ich6-gpio";
186 u-boot,dm-pre-reloc;
187 reg = <0x40 0x20>;
188 bank-name = "C";
189 };
190
191 gpiod {
192 compatible = "intel,ich6-gpio";
193 u-boot,dm-pre-reloc;
194 reg = <0x60 0x20>;
195 bank-name = "D";
196 };
197
198 gpioe {
199 compatible = "intel,ich6-gpio";
200 u-boot,dm-pre-reloc;
201 reg = <0x80 0x20>;
202 bank-name = "E";
203 };
204
205 gpiof {
206 compatible = "intel,ich6-gpio";
207 u-boot,dm-pre-reloc;
208 reg = <0xA0 0x20>;
209 bank-name = "F";
210 };
211 };
212 };
213
214 fsp {
215 compatible = "intel,baytrail-fsp";
216 fsp,mrc-init-tseg-size = <0>;
217 fsp,mrc-init-mmio-size = <0x800>;
218 fsp,mrc-init-spd-addr1 = <0xa0>;
219 fsp,mrc-init-spd-addr2 = <0xa2>;
220 fsp,emmc-boot-mode = <2>;
221 fsp,enable-sdio;
222 fsp,enable-sdcard;
223 fsp,enable-hsuart1;
224 fsp,enable-spi;
225 fsp,enable-sata;
226 fsp,sata-mode = <1>;
227 fsp,enable-lpe;
228 fsp,lpss-sio-enable-pci-mode;
229 fsp,enable-dma0;
230 fsp,enable-dma1;
231 fsp,enable-i2c0;
232 fsp,enable-i2c1;
233 fsp,enable-i2c2;
234 fsp,enable-i2c3;
235 fsp,enable-i2c4;
236 fsp,enable-i2c5;
237 fsp,enable-i2c6;
238 fsp,enable-pwm0;
239 fsp,enable-pwm1;
240 fsp,igd-dvmt50-pre-alloc = <2>;
241 fsp,aperture-size = <2>;
242 fsp,gtt-size = <2>;
243 fsp,scc-enable-pci-mode;
244 fsp,os-selection = <4>;
245 fsp,emmc45-ddr50-enabled;
246 fsp,emmc45-retune-timer-value = <8>;
247 fsp,enable-igd;
248 fsp,enable-memory-down;
249 fsp,memory-down-params {
250 compatible = "intel,baytrail-fsp-mdp";
251 fsp,dram-speed = <2>; /* 2=1333MHz */
252 fsp,dram-type = <1>; /* 1=DDR3L */
253 fsp,dimm-0-enable;
254 fsp,dimm-1-enable;
255 fsp,dimm-width = <1>; /* 1=x16, 2=x32 */
256 fsp,dimm-density = <2>; /* 2=4Gbit */
257 fsp,dimm-bus-width = <3>; /* 3=64bits */
258 fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */
259
260 /* These following values might need a re-visit */
261 fsp,dimm-tcl = <8>;
262 fsp,dimm-trpt-rcd = <8>;
263 fsp,dimm-twr = <8>;
264 fsp,dimm-twtr = <4>;
265 fsp,dimm-trrd = <6>;
266 fsp,dimm-trtp = <4>;
267 fsp,dimm-tfaw = <22>;
268 };
269 };
270
271 microcode {
272 update@0 {
Bin Mengae864552016-05-23 15:25:20 +0800[diff] [blame]273#include "microcode/m0130673325.dtsi"
Stefan Roese2a0b94c2016-03-16 08:48:21 +0100[diff] [blame]274 };
275 update@1 {
Bin Mengae864552016-05-23 15:25:20 +0800[diff] [blame]276#include "microcode/m0130679907.dtsi"
Stefan Roese2a0b94c2016-03-16 08:48:21 +0100[diff] [blame]277 };
278 };
279};