Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 2 | /* |
| 3 | * NVIDIA Tegra SPI controller (T114 and later) |
| 4 | * |
| 5 | * Copyright (c) 2010-2013 NVIDIA Corporation |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 9 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Simon Glass | 495a5dc | 2019-11-14 12:57:30 -0700 | [diff] [blame] | 11 | #include <time.h> |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 12 | #include <asm/io.h> |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 13 | #include <asm/arch/clock.h> |
| 14 | #include <asm/arch-tegra/clk_rst.h> |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 15 | #include <spi.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 16 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 17 | #include <linux/delay.h> |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 18 | #include "tegra_spi.h" |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 19 | |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 20 | /* COMMAND1 */ |
Jagan Teki | 7f7ccf7 | 2015-10-23 01:39:06 +0530 | [diff] [blame] | 21 | #define SPI_CMD1_GO BIT(31) |
| 22 | #define SPI_CMD1_M_S BIT(30) |
Jagan Teki | 54badcb | 2015-10-23 01:03:10 +0530 | [diff] [blame] | 23 | #define SPI_CMD1_MODE_MASK GENMASK(1, 0) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 24 | #define SPI_CMD1_MODE_SHIFT 28 |
Jagan Teki | 54badcb | 2015-10-23 01:03:10 +0530 | [diff] [blame] | 25 | #define SPI_CMD1_CS_SEL_MASK GENMASK(1, 0) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 26 | #define SPI_CMD1_CS_SEL_SHIFT 26 |
Jagan Teki | 7f7ccf7 | 2015-10-23 01:39:06 +0530 | [diff] [blame] | 27 | #define SPI_CMD1_CS_POL_INACTIVE3 BIT(25) |
| 28 | #define SPI_CMD1_CS_POL_INACTIVE2 BIT(24) |
| 29 | #define SPI_CMD1_CS_POL_INACTIVE1 BIT(23) |
| 30 | #define SPI_CMD1_CS_POL_INACTIVE0 BIT(22) |
| 31 | #define SPI_CMD1_CS_SW_HW BIT(21) |
| 32 | #define SPI_CMD1_CS_SW_VAL BIT(20) |
Jagan Teki | 54badcb | 2015-10-23 01:03:10 +0530 | [diff] [blame] | 33 | #define SPI_CMD1_IDLE_SDA_MASK GENMASK(1, 0) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 34 | #define SPI_CMD1_IDLE_SDA_SHIFT 18 |
Jagan Teki | 7f7ccf7 | 2015-10-23 01:39:06 +0530 | [diff] [blame] | 35 | #define SPI_CMD1_BIDIR BIT(17) |
| 36 | #define SPI_CMD1_LSBI_FE BIT(16) |
| 37 | #define SPI_CMD1_LSBY_FE BIT(15) |
| 38 | #define SPI_CMD1_BOTH_EN_BIT BIT(14) |
| 39 | #define SPI_CMD1_BOTH_EN_BYTE BIT(13) |
| 40 | #define SPI_CMD1_RX_EN BIT(12) |
| 41 | #define SPI_CMD1_TX_EN BIT(11) |
| 42 | #define SPI_CMD1_PACKED BIT(5) |
Jagan Teki | 54badcb | 2015-10-23 01:03:10 +0530 | [diff] [blame] | 43 | #define SPI_CMD1_BIT_LEN_MASK GENMASK(4, 0) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 44 | #define SPI_CMD1_BIT_LEN_SHIFT 0 |
| 45 | |
| 46 | /* COMMAND2 */ |
Jagan Teki | 7f7ccf7 | 2015-10-23 01:39:06 +0530 | [diff] [blame] | 47 | #define SPI_CMD2_TX_CLK_TAP_DELAY BIT(6) |
Jagan Teki | 54badcb | 2015-10-23 01:03:10 +0530 | [diff] [blame] | 48 | #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11, 6) |
Jagan Teki | 7f7ccf7 | 2015-10-23 01:39:06 +0530 | [diff] [blame] | 49 | #define SPI_CMD2_RX_CLK_TAP_DELAY BIT(0) |
Jagan Teki | 54badcb | 2015-10-23 01:03:10 +0530 | [diff] [blame] | 50 | #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5, 0) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 51 | |
| 52 | /* TRANSFER STATUS */ |
Jagan Teki | 7f7ccf7 | 2015-10-23 01:39:06 +0530 | [diff] [blame] | 53 | #define SPI_XFER_STS_RDY BIT(30) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 54 | |
| 55 | /* FIFO STATUS */ |
Jagan Teki | 7f7ccf7 | 2015-10-23 01:39:06 +0530 | [diff] [blame] | 56 | #define SPI_FIFO_STS_CS_INACTIVE BIT(31) |
| 57 | #define SPI_FIFO_STS_FRAME_END BIT(30) |
| 58 | #define SPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) |
| 59 | #define SPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) |
| 60 | #define SPI_FIFO_STS_ERR BIT(8) |
| 61 | #define SPI_FIFO_STS_TX_FIFO_OVF BIT(7) |
| 62 | #define SPI_FIFO_STS_TX_FIFO_UNR BIT(6) |
| 63 | #define SPI_FIFO_STS_RX_FIFO_OVF BIT(5) |
| 64 | #define SPI_FIFO_STS_RX_FIFO_UNR BIT(4) |
| 65 | #define SPI_FIFO_STS_TX_FIFO_FULL BIT(3) |
| 66 | #define SPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) |
| 67 | #define SPI_FIFO_STS_RX_FIFO_FULL BIT(1) |
| 68 | #define SPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 69 | |
| 70 | #define SPI_TIMEOUT 1000 |
| 71 | #define TEGRA_SPI_MAX_FREQ 52000000 |
| 72 | |
| 73 | struct spi_regs { |
| 74 | u32 command1; /* 000:SPI_COMMAND1 register */ |
| 75 | u32 command2; /* 004:SPI_COMMAND2 register */ |
| 76 | u32 timing1; /* 008:SPI_CS_TIM1 register */ |
| 77 | u32 timing2; /* 00c:SPI_CS_TIM2 register */ |
| 78 | u32 xfer_status;/* 010:SPI_TRANS_STATUS register */ |
| 79 | u32 fifo_status;/* 014:SPI_FIFO_STATUS register */ |
| 80 | u32 tx_data; /* 018:SPI_TX_DATA register */ |
| 81 | u32 rx_data; /* 01c:SPI_RX_DATA register */ |
| 82 | u32 dma_ctl; /* 020:SPI_DMA_CTL register */ |
| 83 | u32 dma_blk; /* 024:SPI_DMA_BLK register */ |
| 84 | u32 rsvd[56]; /* 028-107 reserved */ |
| 85 | u32 tx_fifo; /* 108:SPI_FIFO1 register */ |
| 86 | u32 rsvd2[31]; /* 10c-187 reserved */ |
| 87 | u32 rx_fifo; /* 188:SPI_FIFO2 register */ |
| 88 | u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ |
| 89 | }; |
| 90 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 91 | struct tegra114_spi_priv { |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 92 | struct spi_regs *regs; |
| 93 | unsigned int freq; |
| 94 | unsigned int mode; |
| 95 | int periph_id; |
| 96 | int valid; |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 97 | int last_transaction_us; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 98 | }; |
| 99 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 100 | static int tegra114_spi_of_to_plat(struct udevice *bus) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 101 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 102 | struct tegra_spi_plat *plat = dev_get_plat(bus); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 103 | |
Simon Glass | 3f738a2 | 2017-07-25 08:30:05 -0600 | [diff] [blame] | 104 | plat->base = dev_read_addr(bus); |
Simon Glass | c3f2650 | 2017-07-25 08:30:00 -0600 | [diff] [blame] | 105 | plat->periph_id = clock_decode_periph_id(bus); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 106 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 107 | if (plat->periph_id == PERIPH_ID_NONE) { |
| 108 | debug("%s: could not decode periph id %d\n", __func__, |
| 109 | plat->periph_id); |
| 110 | return -FDT_ERR_NOTFOUND; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 111 | } |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 112 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 113 | /* Use 500KHz as a suitable default */ |
Simon Glass | 3f738a2 | 2017-07-25 08:30:05 -0600 | [diff] [blame] | 114 | plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", |
| 115 | 500000); |
| 116 | plat->deactivate_delay_us = dev_read_u32_default(bus, |
| 117 | "spi-deactivate-delay", 0); |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 118 | debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", |
| 119 | __func__, plat->base, plat->periph_id, plat->frequency, |
| 120 | plat->deactivate_delay_us); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 121 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 122 | return 0; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 123 | } |
| 124 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 125 | static int tegra114_spi_probe(struct udevice *bus) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 126 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 127 | struct tegra_spi_plat *plat = dev_get_plat(bus); |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 128 | struct tegra114_spi_priv *priv = dev_get_priv(bus); |
Simon Glass | f669ba4 | 2015-06-05 14:39:33 -0600 | [diff] [blame] | 129 | struct spi_regs *regs; |
Simon Glass | c1865a5 | 2015-06-05 14:39:35 -0600 | [diff] [blame] | 130 | ulong rate; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 131 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 132 | priv->regs = (struct spi_regs *)plat->base; |
Simon Glass | f669ba4 | 2015-06-05 14:39:33 -0600 | [diff] [blame] | 133 | regs = priv->regs; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 134 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 135 | priv->last_transaction_us = timer_get_us(); |
| 136 | priv->freq = plat->frequency; |
| 137 | priv->periph_id = plat->periph_id; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 138 | |
Simon Glass | c1865a5 | 2015-06-05 14:39:35 -0600 | [diff] [blame] | 139 | /* |
| 140 | * Change SPI clock to correct frequency, PLLP_OUT0 source, falling |
| 141 | * back to the oscillator if that is too fast. |
| 142 | */ |
| 143 | rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, |
| 144 | priv->freq); |
| 145 | if (rate > priv->freq + 100000) { |
| 146 | rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC, |
| 147 | priv->freq); |
| 148 | if (rate != priv->freq) { |
| 149 | printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n", |
| 150 | bus->name, priv->freq, rate); |
| 151 | } |
| 152 | } |
Simon Glass | 4812d4c | 2017-05-31 17:57:18 -0600 | [diff] [blame] | 153 | udelay(plat->deactivate_delay_us); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 154 | |
| 155 | /* Clear stale status here */ |
| 156 | setbits_le32(®s->fifo_status, |
| 157 | SPI_FIFO_STS_ERR | |
| 158 | SPI_FIFO_STS_TX_FIFO_OVF | |
| 159 | SPI_FIFO_STS_TX_FIFO_UNR | |
| 160 | SPI_FIFO_STS_RX_FIFO_OVF | |
| 161 | SPI_FIFO_STS_RX_FIFO_UNR | |
| 162 | SPI_FIFO_STS_TX_FIFO_FULL | |
| 163 | SPI_FIFO_STS_TX_FIFO_EMPTY | |
| 164 | SPI_FIFO_STS_RX_FIFO_FULL | |
| 165 | SPI_FIFO_STS_RX_FIFO_EMPTY); |
| 166 | debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); |
| 167 | |
Simon Glass | f669ba4 | 2015-06-05 14:39:33 -0600 | [diff] [blame] | 168 | setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | |
| 169 | (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 170 | debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 175 | /** |
| 176 | * Activate the CS by driving it LOW |
| 177 | * |
| 178 | * @param slave Pointer to spi_slave to which controller has to |
| 179 | * communicate with |
| 180 | */ |
| 181 | static void spi_cs_activate(struct udevice *dev) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 182 | { |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 183 | struct udevice *bus = dev->parent; |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 184 | struct tegra_spi_plat *pdata = dev_get_plat(bus); |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 185 | struct tegra114_spi_priv *priv = dev_get_priv(bus); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 186 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 187 | /* If it's too soon to do another transaction, wait */ |
| 188 | if (pdata->deactivate_delay_us && |
| 189 | priv->last_transaction_us) { |
| 190 | ulong delay_us; /* The delay completed so far */ |
| 191 | delay_us = timer_get_us() - priv->last_transaction_us; |
| 192 | if (delay_us < pdata->deactivate_delay_us) |
| 193 | udelay(pdata->deactivate_delay_us - delay_us); |
| 194 | } |
| 195 | |
| 196 | clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 197 | } |
| 198 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 199 | /** |
| 200 | * Deactivate the CS by driving it HIGH |
| 201 | * |
| 202 | * @param slave Pointer to spi_slave to which controller has to |
| 203 | * communicate with |
| 204 | */ |
| 205 | static void spi_cs_deactivate(struct udevice *dev) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 206 | { |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 207 | struct udevice *bus = dev->parent; |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 208 | struct tegra_spi_plat *pdata = dev_get_plat(bus); |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 209 | struct tegra114_spi_priv *priv = dev_get_priv(bus); |
| 210 | |
| 211 | setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 212 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 213 | /* Remember time of this transaction so we can honour the bus delay */ |
| 214 | if (pdata->deactivate_delay_us) |
| 215 | priv->last_transaction_us = timer_get_us(); |
| 216 | |
| 217 | debug("Deactivate CS, bus '%s'\n", bus->name); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 218 | } |
| 219 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 220 | static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 221 | const void *data_out, void *data_in, |
| 222 | unsigned long flags) |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 223 | { |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 224 | struct udevice *bus = dev->parent; |
| 225 | struct tegra114_spi_priv *priv = dev_get_priv(bus); |
| 226 | struct spi_regs *regs = priv->regs; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 227 | u32 reg, tmpdout, tmpdin = 0; |
| 228 | const u8 *dout = data_out; |
| 229 | u8 *din = data_in; |
| 230 | int num_bytes; |
| 231 | int ret; |
| 232 | |
| 233 | debug("%s: slave %u:%u dout %p din %p bitlen %u\n", |
Simon Glass | 75e534b | 2020-12-16 21:20:07 -0700 | [diff] [blame] | 234 | __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 235 | if (bitlen % 8) |
| 236 | return -1; |
| 237 | num_bytes = bitlen / 8; |
| 238 | |
| 239 | ret = 0; |
| 240 | |
Simon Glass | f669ba4 | 2015-06-05 14:39:33 -0600 | [diff] [blame] | 241 | if (flags & SPI_XFER_BEGIN) |
| 242 | spi_cs_activate(dev); |
| 243 | |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 244 | /* clear all error status bits */ |
| 245 | reg = readl(®s->fifo_status); |
| 246 | writel(reg, ®s->fifo_status); |
| 247 | |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 248 | clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, |
| 249 | SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 250 | (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT)); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 251 | |
| 252 | /* set xfer size to 1 block (32 bits) */ |
| 253 | writel(0, ®s->dma_blk); |
| 254 | |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 255 | /* handle data in 32-bit chunks */ |
| 256 | while (num_bytes > 0) { |
| 257 | int bytes; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 258 | int tm, i; |
| 259 | |
| 260 | tmpdout = 0; |
| 261 | bytes = (num_bytes > 4) ? 4 : num_bytes; |
| 262 | |
| 263 | if (dout != NULL) { |
| 264 | for (i = 0; i < bytes; ++i) |
| 265 | tmpdout = (tmpdout << 8) | dout[i]; |
| 266 | dout += bytes; |
| 267 | } |
| 268 | |
| 269 | num_bytes -= bytes; |
| 270 | |
Yen Lin | 02ca8c2 | 2013-12-18 11:18:46 -0700 | [diff] [blame] | 271 | /* clear ready bit */ |
| 272 | setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); |
| 273 | |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 274 | clrsetbits_le32(®s->command1, |
| 275 | SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, |
| 276 | (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); |
| 277 | writel(tmpdout, ®s->tx_fifo); |
| 278 | setbits_le32(®s->command1, SPI_CMD1_GO); |
| 279 | |
| 280 | /* |
| 281 | * Wait for SPI transmit FIFO to empty, or to time out. |
| 282 | * The RX FIFO status will be read and cleared last |
| 283 | */ |
Yen Lin | 02ca8c2 | 2013-12-18 11:18:46 -0700 | [diff] [blame] | 284 | for (tm = 0; tm < SPI_TIMEOUT; ++tm) { |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 285 | u32 fifo_status, xfer_status; |
| 286 | |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 287 | xfer_status = readl(®s->xfer_status); |
| 288 | if (!(xfer_status & SPI_XFER_STS_RDY)) |
| 289 | continue; |
| 290 | |
Yen Lin | 02ca8c2 | 2013-12-18 11:18:46 -0700 | [diff] [blame] | 291 | fifo_status = readl(®s->fifo_status); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 292 | if (fifo_status & SPI_FIFO_STS_ERR) { |
| 293 | debug("%s: got a fifo error: ", __func__); |
| 294 | if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) |
| 295 | debug("tx FIFO overflow "); |
| 296 | if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR) |
| 297 | debug("tx FIFO underrun "); |
| 298 | if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF) |
| 299 | debug("rx FIFO overflow "); |
| 300 | if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR) |
| 301 | debug("rx FIFO underrun "); |
| 302 | if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL) |
| 303 | debug("tx FIFO full "); |
| 304 | if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY) |
| 305 | debug("tx FIFO empty "); |
| 306 | if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL) |
| 307 | debug("rx FIFO full "); |
| 308 | if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY) |
| 309 | debug("rx FIFO empty "); |
| 310 | debug("\n"); |
| 311 | break; |
| 312 | } |
| 313 | |
| 314 | if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { |
| 315 | tmpdin = readl(®s->rx_fifo); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 316 | |
| 317 | /* swap bytes read in */ |
| 318 | if (din != NULL) { |
| 319 | for (i = bytes - 1; i >= 0; --i) { |
| 320 | din[i] = tmpdin & 0xff; |
| 321 | tmpdin >>= 8; |
| 322 | } |
| 323 | din += bytes; |
| 324 | } |
Yen Lin | 02ca8c2 | 2013-12-18 11:18:46 -0700 | [diff] [blame] | 325 | |
| 326 | /* We can exit when we've had both RX and TX */ |
| 327 | break; |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 328 | } |
| 329 | } |
| 330 | |
| 331 | if (tm >= SPI_TIMEOUT) |
| 332 | ret = tm; |
| 333 | |
| 334 | /* clear ACK RDY, etc. bits */ |
| 335 | writel(readl(®s->fifo_status), ®s->fifo_status); |
| 336 | } |
| 337 | |
| 338 | if (flags & SPI_XFER_END) |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 339 | spi_cs_deactivate(dev); |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 340 | |
| 341 | debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", |
| 342 | __func__, tmpdin, readl(®s->fifo_status)); |
| 343 | |
| 344 | if (ret) { |
| 345 | printf("%s: timeout during SPI transfer, tm %d\n", |
| 346 | __func__, ret); |
| 347 | return -1; |
| 348 | } |
| 349 | |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 350 | return ret; |
| 351 | } |
| 352 | |
| 353 | static int tegra114_spi_set_speed(struct udevice *bus, uint speed) |
| 354 | { |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 355 | struct tegra_spi_plat *plat = dev_get_plat(bus); |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 356 | struct tegra114_spi_priv *priv = dev_get_priv(bus); |
| 357 | |
| 358 | if (speed > plat->frequency) |
| 359 | speed = plat->frequency; |
| 360 | priv->freq = speed; |
| 361 | debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); |
| 362 | |
Allen Martin | 21f5b93 | 2013-03-16 18:58:13 +0000 | [diff] [blame] | 363 | return 0; |
| 364 | } |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 365 | |
| 366 | static int tegra114_spi_set_mode(struct udevice *bus, uint mode) |
| 367 | { |
| 368 | struct tegra114_spi_priv *priv = dev_get_priv(bus); |
| 369 | |
| 370 | priv->mode = mode; |
| 371 | debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); |
| 372 | |
| 373 | return 0; |
| 374 | } |
| 375 | |
| 376 | static const struct dm_spi_ops tegra114_spi_ops = { |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 377 | .xfer = tegra114_spi_xfer, |
| 378 | .set_speed = tegra114_spi_set_speed, |
| 379 | .set_mode = tegra114_spi_set_mode, |
| 380 | /* |
| 381 | * cs_info is not needed, since we require all chip selects to be |
| 382 | * in the device tree explicitly |
| 383 | */ |
| 384 | }; |
| 385 | |
| 386 | static const struct udevice_id tegra114_spi_ids[] = { |
| 387 | { .compatible = "nvidia,tegra114-spi" }, |
| 388 | { } |
| 389 | }; |
| 390 | |
| 391 | U_BOOT_DRIVER(tegra114_spi) = { |
| 392 | .name = "tegra114_spi", |
| 393 | .id = UCLASS_SPI, |
| 394 | .of_match = tegra114_spi_ids, |
| 395 | .ops = &tegra114_spi_ops, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 396 | .of_to_plat = tegra114_spi_of_to_plat, |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 397 | .plat_auto = sizeof(struct tegra_spi_plat), |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 398 | .priv_auto = sizeof(struct tegra114_spi_priv), |
Simon Glass | 1121b1b | 2014-10-13 23:42:13 -0600 | [diff] [blame] | 399 | .probe = tegra114_spi_probe, |
| 400 | }; |