| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 |
| 4 | * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com> |
| 5 | * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com> |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 11 | #define CONFIG_HOSTNAME "kmcoge5ne" |
| Holger Brunck | 154772c | 2013-01-21 03:55:23 +0000 | [diff] [blame] | 12 | #define CONFIG_NAND_ECC_BCH |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 13 | #define CONFIG_NAND_KMETER1 |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 14 | #define NAND_MAX_CHIPS 1 |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 15 | #define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 16 | |
| 17 | #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" |
| 18 | #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 19 | |
| Mario Six | cb791a8 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 20 | /* include common defines/options for all Keymile boards */ |
| 21 | #include "km/keymile-common.h" |
| 22 | #include "km/km-powerpc.h" |
| Mario Six | 3e67cb2 | 2019-01-21 09:18:23 +0100 | [diff] [blame] | 23 | #include "km/km-mpc83xx.h" |
| 24 | #include "km/km-mpc8360.h" |
| Mario Six | cb791a8 | 2019-01-21 09:17:34 +0100 | [diff] [blame] | 25 | |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 26 | /** |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 27 | * KMCOGE5NE has 512 MB RAM |
| 28 | */ |
| 29 | #define CONFIG_SYS_DDR_CS0_CONFIG (\ |
| 30 | CSCONFIG_EN | \ |
| 31 | CSCONFIG_AP | \ |
| Valentin Longchamp | 9c36b47 | 2015-11-17 10:53:33 +0100 | [diff] [blame] | 32 | CSCONFIG_ODT_WR_ONLY_CURRENT | \ |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 33 | CSCONFIG_BANK_BIT_3 | \ |
| 34 | CSCONFIG_ROW_BIT_13 | \ |
| 35 | CSCONFIG_COL_BIT_10) |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 36 | |
| Thomas Herzmann | 94fbf52 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 37 | /* enable POST tests */ |
| 38 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) |
| 39 | #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ |
| Holger Brunck | 108ce1b | 2020-10-29 13:54:54 +0100 | [diff] [blame] | 40 | #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END |
| Thomas Herzmann | 94fbf52 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 41 | #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ |
| 42 | #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ |
| Thomas Herzmann | 94fbf52 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 43 | |
| Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 44 | #endif /* CONFIG */ |