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git01.mediatek.com / filogic / uboot / ff2120515865d81b3e7609b7ccad7fd9ffd0de10 / . / include / video_ad7176.h
blob: 6a0230e5a1bde963eb9e7928c00a62b8e4517874 [file] [log] [blame]
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]6 */
7
8#ifndef _VIDEO_AD7176_H_
9#define _VIDEO_AD7176_H_
10
11#define VIDEO_ENCODER_NAME "Analog Devices AD7176"
12
wdenkdccbda02003-07-14 22:13:32 +0000[diff] [blame]13#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]14#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
15
wdenkdccbda02003-07-14 22:13:32 +0000[diff] [blame]16#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
17#undef VIDEO_MODE_RGB
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]18#define VIDEO_MODE_BPP 16
19
wdenkdccbda02003-07-14 22:13:32 +0000[diff] [blame]20#ifdef VIDEO_MODE_PAL
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]21#define VIDEO_ACTIVE_COLS 720
22#define VIDEO_ACTIVE_ROWS 576
23#define VIDEO_VISIBLE_COLS 640
24#define VIDEO_VISIBLE_ROWS 480
25#endif
26
wdenkdccbda02003-07-14 22:13:32 +0000[diff] [blame]27#ifdef VIDEO_MODE_NTSC
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]28#define VIDEO_ACTIVE_COLS 720
29#define VIDEO_ACTIVE_ROWS 525
30#define VIDEO_VISIBLE_COLS 640
31#define VIDEO_VISIBLE_ROWS 400
32#endif
33
34static unsigned char video_encoder_data[] = {
35#ifdef VIDEO_MODE_NTSC
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]36 0x04, /* Mode Register 0 */
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]37#ifdef VIDEO_DEBUG_COLORBARS
38 0x82,
39#else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]40 0x02, /* Mode Register 1 */
wdenkdccbda02003-07-14 22:13:32 +0000[diff] [blame]41#endif /* VIDEO_DEBUG_COLORBARS */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]42 0x16, /* Subcarrier Freq 0 */
43 0x7c, /* Subcarrier Freq 1 */
44 0xf0, /* Subcarrier Freq 2 */
45 0x21, /* Subcarrier Freq 3 */
46 0x00, /* Subcarrier phase */
47 0x02, /* Timing Register 0 */
48 0x00, /* Extended Captioning 0 */
49 0x00, /* Extended Captioning 1 */
50 0x00, /* Closed Captioning 0 */
51 0x00, /* Closed Captioning 1 */
52 0x00, /* Timing Register 1 */
53 0x08, /* Mode Register 2 */
54 0x00, /* Pedestal Register 0 */
55 0x00, /* Pedestal Register 1 */
56 0x00, /* Pedestal Register 2 */
57 0x00, /* Pedestal Register 3 */
58 0x00 /* Mode Register 3 */
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]59
60#endif /* VIDEO_MODE_NTSC */
61
62#ifdef VIDEO_MODE_PAL
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]63 0x05, /* Mode Register 0 */
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]64#ifdef VIDEO_DEBUG_COLORBARS
65 0x82,
66#else
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]67 0x02, /* Mode Register 1 (2) */
wdenkdccbda02003-07-14 22:13:32 +0000[diff] [blame]68#endif /* VIDEO_DEBUG_COLORBARS */
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]69 0xcb, /* Subcarrier Freq 0 */
70 0x8a, /* Subcarrier Freq 1 */
71 0x09, /* Subcarrier Freq 2 */
72 0x2a, /* Subcarrier Freq 3 */
73 0x00, /* Subcarrier phase */
74 0x0a, /* Timing Register 0 (a) */
75 0x00, /* Extended Captioning 0 */
76 0x00, /* Extended Captioning 1 */
77 0x00, /* Closed Captioning 0 */
78 0x00, /* Closed Captioning 1 */
79 0x00, /* Timing Register 1 */
80 0x08, /* Mode Register 2 (8) */
81 0x00, /* Pedestal Register 0 */
82 0x00, /* Pedestal Register 1 */
83 0x00, /* Pedestal Register 2 */
84 0x00, /* Pedestal Register 3 */
85 0x00 /* Mode Register 3 */
wdenk5eefc952002-10-21 18:54:49 +0000[diff] [blame]86#endif /* VIDEO_MODE_PAL */
87} ;
88
89#endif /* _VIDEO_AD7176_H_ */