Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2015 Google, Inc |
| 4 | * Copyright 2014 Rockchip Inc. |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <clk.h> |
| 9 | #include <display.h> |
| 10 | #include <dm.h> |
| 11 | #include <edid.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 13 | #include <malloc.h> |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 14 | #include <panel.h> |
| 15 | #include <regmap.h> |
| 16 | #include <syscon.h> |
| 17 | #include <asm/gpio.h> |
| 18 | #include <asm/io.h> |
Kever Yang | 9fbe17c | 2019-03-28 11:01:23 +0800 | [diff] [blame] | 19 | #include <asm/arch-rockchip/clock.h> |
| 20 | #include <asm/arch-rockchip/edp_rk3288.h> |
| 21 | #include <asm/arch-rockchip/grf_rk3288.h> |
Peter Robinson | 07c7876 | 2020-04-20 19:18:25 +0100 | [diff] [blame] | 22 | #include <asm/arch-rockchip/hardware.h> |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 23 | #include <dt-bindings/clock/rk3288-cru.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 24 | #include <linux/delay.h> |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 25 | |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 26 | #define MAX_CR_LOOP 5 |
| 27 | #define MAX_EQ_LOOP 5 |
| 28 | #define DP_LINK_STATUS_SIZE 6 |
| 29 | |
| 30 | static const char * const voltage_names[] = { |
| 31 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 32 | }; |
| 33 | static const char * const pre_emph_names[] = { |
| 34 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 35 | }; |
| 36 | |
| 37 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
| 38 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
| 39 | |
| 40 | struct rk_edp_priv { |
| 41 | struct rk3288_edp *regs; |
| 42 | struct rk3288_grf *grf; |
| 43 | struct udevice *panel; |
| 44 | struct link_train link_train; |
| 45 | u8 train_set[4]; |
| 46 | }; |
| 47 | |
| 48 | static void rk_edp_init_refclk(struct rk3288_edp *regs) |
| 49 | { |
| 50 | writel(SEL_24M, ®s->analog_ctl_2); |
| 51 | writel(REF_CLK_24M, ®s->pll_reg_1); |
| 52 | |
| 53 | writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US | |
| 54 | V2L_CUR_SEL_1MA, ®s->pll_reg_2); |
| 55 | |
| 56 | writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET | |
| 57 | LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE, |
| 58 | ®s->pll_reg_3); |
| 59 | |
| 60 | writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL | |
| 61 | CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP, |
| 62 | ®s->pll_reg_5); |
| 63 | |
| 64 | writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg); |
| 65 | |
| 66 | writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 | |
| 67 | LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL, |
| 68 | ®s->tx_common); |
| 69 | |
| 70 | writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM, |
| 71 | ®s->dp_aux); |
| 72 | |
| 73 | writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG, |
| 74 | ®s->dp_bias); |
| 75 | |
| 76 | writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL, |
| 77 | ®s->dp_reserv2); |
| 78 | } |
| 79 | |
| 80 | static void rk_edp_init_interrupt(struct rk3288_edp *regs) |
| 81 | { |
| 82 | /* Set interrupt pin assertion polarity as high */ |
| 83 | writel(INT_POL, ®s->int_ctl); |
| 84 | |
| 85 | /* Clear pending registers */ |
| 86 | writel(0xff, ®s->common_int_sta_1); |
| 87 | writel(0x4f, ®s->common_int_sta_2); |
| 88 | writel(0xff, ®s->common_int_sta_3); |
| 89 | writel(0x27, ®s->common_int_sta_4); |
| 90 | writel(0x7f, ®s->dp_int_sta); |
| 91 | |
| 92 | /* 0:mask,1: unmask */ |
| 93 | writel(0x00, ®s->common_int_mask_1); |
| 94 | writel(0x00, ®s->common_int_mask_2); |
| 95 | writel(0x00, ®s->common_int_mask_3); |
| 96 | writel(0x00, ®s->common_int_mask_4); |
| 97 | writel(0x00, ®s->int_sta_mask); |
| 98 | } |
| 99 | |
| 100 | static void rk_edp_enable_sw_function(struct rk3288_edp *regs) |
| 101 | { |
| 102 | clrbits_le32(®s->func_en_1, SW_FUNC_EN_N); |
| 103 | } |
| 104 | |
| 105 | static bool rk_edp_get_pll_locked(struct rk3288_edp *regs) |
| 106 | { |
| 107 | u32 val; |
| 108 | |
| 109 | val = readl(®s->dp_debug_ctl); |
| 110 | |
| 111 | return val & PLL_LOCK; |
| 112 | } |
| 113 | |
| 114 | static int rk_edp_init_analog_func(struct rk3288_edp *regs) |
| 115 | { |
| 116 | ulong start; |
| 117 | |
| 118 | writel(0x00, ®s->dp_pd); |
| 119 | writel(PLL_LOCK_CHG, ®s->common_int_sta_1); |
| 120 | |
| 121 | clrbits_le32(®s->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); |
| 122 | |
| 123 | start = get_timer(0); |
| 124 | while (!rk_edp_get_pll_locked(regs)) { |
| 125 | if (get_timer(start) > PLL_LOCK_TIMEOUT) { |
| 126 | printf("%s: PLL is not locked\n", __func__); |
| 127 | return -ETIMEDOUT; |
| 128 | } |
| 129 | } |
| 130 | |
| 131 | /* Enable Serdes FIFO function and Link symbol clock domain module */ |
| 132 | clrbits_le32(®s->func_en_2, SERDES_FIFO_FUNC_EN_N | |
| 133 | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N | |
| 134 | SSC_FUNC_EN_N); |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | static void rk_edp_init_aux(struct rk3288_edp *regs) |
| 140 | { |
| 141 | /* Clear inerrupts related to AUX channel */ |
| 142 | writel(AUX_FUNC_EN_N, ®s->dp_int_sta); |
| 143 | |
| 144 | /* Disable AUX channel module */ |
| 145 | setbits_le32(®s->func_en_2, AUX_FUNC_EN_N); |
| 146 | |
| 147 | /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ |
| 148 | writel(DEFER_CTRL_EN | DEFER_COUNT(1), ®s->aux_ch_defer_dtl); |
| 149 | |
| 150 | /* Enable AUX channel module */ |
| 151 | clrbits_le32(®s->func_en_2, AUX_FUNC_EN_N); |
| 152 | } |
| 153 | |
| 154 | static int rk_edp_aux_enable(struct rk3288_edp *regs) |
| 155 | { |
| 156 | ulong start; |
| 157 | |
| 158 | setbits_le32(®s->aux_ch_ctl_2, AUX_EN); |
| 159 | start = get_timer(0); |
| 160 | do { |
| 161 | if (!(readl(®s->aux_ch_ctl_2) & AUX_EN)) |
| 162 | return 0; |
| 163 | } while (get_timer(start) < 20); |
| 164 | |
| 165 | return -ETIMEDOUT; |
| 166 | } |
| 167 | |
| 168 | static int rk_edp_is_aux_reply(struct rk3288_edp *regs) |
| 169 | { |
| 170 | ulong start; |
| 171 | |
| 172 | start = get_timer(0); |
| 173 | while (!(readl(®s->dp_int_sta) & RPLY_RECEIV)) { |
| 174 | if (get_timer(start) > 10) |
| 175 | return -ETIMEDOUT; |
| 176 | } |
| 177 | |
| 178 | writel(RPLY_RECEIV, ®s->dp_int_sta); |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
| 183 | static int rk_edp_start_aux_transaction(struct rk3288_edp *regs) |
| 184 | { |
| 185 | int val, ret; |
| 186 | |
| 187 | /* Enable AUX CH operation */ |
| 188 | ret = rk_edp_aux_enable(regs); |
| 189 | if (ret) { |
| 190 | debug("AUX CH enable timeout!\n"); |
| 191 | return ret; |
| 192 | } |
| 193 | |
| 194 | /* Is AUX CH command reply received? */ |
| 195 | if (rk_edp_is_aux_reply(regs)) { |
| 196 | debug("AUX CH command reply failed!\n"); |
| 197 | return ret; |
| 198 | } |
| 199 | |
| 200 | /* Clear interrupt source for AUX CH access error */ |
| 201 | val = readl(®s->dp_int_sta); |
| 202 | if (val & AUX_ERR) { |
| 203 | writel(AUX_ERR, ®s->dp_int_sta); |
| 204 | return -EIO; |
| 205 | } |
| 206 | |
| 207 | /* Check AUX CH error access status */ |
| 208 | val = readl(®s->dp_int_sta); |
| 209 | if (val & AUX_STATUS_MASK) { |
| 210 | debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK); |
| 211 | return -EIO; |
| 212 | } |
| 213 | |
| 214 | return 0; |
| 215 | } |
| 216 | |
| 217 | static int rk_edp_dpcd_transfer(struct rk3288_edp *regs, |
| 218 | unsigned int val_addr, u8 *in_data, |
| 219 | unsigned int length, |
| 220 | enum dpcd_request request) |
| 221 | { |
| 222 | int val; |
| 223 | int i, try_times; |
| 224 | u8 *data; |
| 225 | int ret = 0; |
| 226 | u32 len = 0; |
| 227 | |
| 228 | while (length) { |
| 229 | len = min(length, 16U); |
| 230 | for (try_times = 0; try_times < 10; try_times++) { |
| 231 | data = in_data; |
| 232 | /* Clear AUX CH data buffer */ |
| 233 | writel(BUF_CLR, ®s->buf_data_ctl); |
| 234 | |
| 235 | /* Select DPCD device address */ |
| 236 | writel(AUX_ADDR_7_0(val_addr), ®s->aux_addr_7_0); |
| 237 | writel(AUX_ADDR_15_8(val_addr), ®s->aux_addr_15_8); |
| 238 | writel(AUX_ADDR_19_16(val_addr), ®s->aux_addr_19_16); |
| 239 | |
| 240 | /* |
| 241 | * Set DisplayPort transaction and read 1 byte |
| 242 | * If bit 3 is 1, DisplayPort transaction. |
| 243 | * If Bit 3 is 0, I2C transaction. |
| 244 | */ |
| 245 | if (request == DPCD_WRITE) { |
| 246 | val = AUX_LENGTH(len) | |
| 247 | AUX_TX_COMM_DP_TRANSACTION | |
| 248 | AUX_TX_COMM_WRITE; |
| 249 | for (i = 0; i < len; i++) |
| 250 | writel(*data++, ®s->buf_data[i]); |
| 251 | } else |
| 252 | val = AUX_LENGTH(len) | |
| 253 | AUX_TX_COMM_DP_TRANSACTION | |
| 254 | AUX_TX_COMM_READ; |
| 255 | |
| 256 | writel(val, ®s->aux_ch_ctl_1); |
| 257 | |
| 258 | /* Start AUX transaction */ |
| 259 | ret = rk_edp_start_aux_transaction(regs); |
| 260 | if (ret == 0) |
| 261 | break; |
| 262 | else |
| 263 | printf("read dpcd Aux Transaction fail!\n"); |
| 264 | } |
| 265 | |
| 266 | if (ret) |
| 267 | return ret; |
| 268 | |
| 269 | if (request == DPCD_READ) { |
| 270 | for (i = 0; i < len; i++) |
| 271 | *data++ = (u8)readl(®s->buf_data[i]); |
| 272 | } |
| 273 | |
| 274 | length -= len; |
| 275 | val_addr += len; |
| 276 | in_data += len; |
| 277 | } |
| 278 | |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values, |
| 283 | size_t size) |
| 284 | { |
| 285 | return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ); |
| 286 | } |
| 287 | |
| 288 | static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values, |
| 289 | size_t size) |
| 290 | { |
| 291 | return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE); |
| 292 | } |
| 293 | |
| 294 | |
| 295 | static int rk_edp_link_power_up(struct rk_edp_priv *edp) |
| 296 | { |
| 297 | u8 value; |
| 298 | int ret; |
| 299 | |
| 300 | /* DP_SET_POWER register is only available on DPCD v1.1 and later */ |
| 301 | if (edp->link_train.revision < 0x11) |
| 302 | return 0; |
| 303 | |
| 304 | ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1); |
| 305 | if (ret) |
| 306 | return ret; |
| 307 | |
| 308 | value &= ~DP_SET_POWER_MASK; |
| 309 | value |= DP_SET_POWER_D0; |
| 310 | |
| 311 | ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1); |
| 312 | if (ret) |
| 313 | return ret; |
| 314 | |
| 315 | /* |
| 316 | * According to the DP 1.1 specification, a "Sink Device must exit the |
| 317 | * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink |
| 318 | * Control Field" (register 0x600). |
| 319 | */ |
| 320 | mdelay(1); |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static int rk_edp_link_configure(struct rk_edp_priv *edp) |
| 326 | { |
| 327 | u8 values[2]; |
| 328 | |
| 329 | values[0] = edp->link_train.link_rate; |
| 330 | values[1] = edp->link_train.lane_count; |
| 331 | |
| 332 | return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values, |
| 333 | sizeof(values)); |
| 334 | } |
| 335 | |
| 336 | static void rk_edp_set_link_training(struct rk_edp_priv *edp, |
| 337 | const u8 *training_values) |
| 338 | { |
| 339 | int i; |
| 340 | |
| 341 | for (i = 0; i < edp->link_train.lane_count; i++) |
| 342 | writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]); |
| 343 | } |
| 344 | |
| 345 | static u8 edp_link_status(const u8 *link_status, int r) |
| 346 | { |
| 347 | return link_status[r - DPCD_LANE0_1_STATUS]; |
| 348 | } |
| 349 | |
| 350 | static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp, |
| 351 | u8 *link_status) |
| 352 | { |
| 353 | return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status, |
| 354 | DP_LINK_STATUS_SIZE); |
| 355 | } |
| 356 | |
| 357 | static u8 edp_get_lane_status(const u8 *link_status, int lane) |
| 358 | { |
| 359 | int i = DPCD_LANE0_1_STATUS + (lane >> 1); |
| 360 | int s = (lane & 1) * 4; |
| 361 | u8 l = edp_link_status(link_status, i); |
| 362 | |
| 363 | return (l >> s) & 0xf; |
| 364 | } |
| 365 | |
| 366 | static int rk_edp_clock_recovery(const u8 *link_status, int lane_count) |
| 367 | { |
| 368 | int lane; |
| 369 | u8 lane_status; |
| 370 | |
| 371 | for (lane = 0; lane < lane_count; lane++) { |
| 372 | lane_status = edp_get_lane_status(link_status, lane); |
| 373 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
| 374 | return -EIO; |
| 375 | } |
| 376 | |
| 377 | return 0; |
| 378 | } |
| 379 | |
| 380 | static int rk_edp_channel_eq(const u8 *link_status, int lane_count) |
| 381 | { |
| 382 | u8 lane_align; |
| 383 | u8 lane_status; |
| 384 | int lane; |
| 385 | |
| 386 | lane_align = edp_link_status(link_status, |
| 387 | DPCD_LANE_ALIGN_STATUS_UPDATED); |
| 388 | if (!(lane_align & DP_INTERLANE_ALIGN_DONE)) |
| 389 | return -EIO; |
| 390 | for (lane = 0; lane < lane_count; lane++) { |
| 391 | lane_status = edp_get_lane_status(link_status, lane); |
| 392 | if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) |
| 393 | return -EIO; |
| 394 | } |
| 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane) |
| 400 | { |
| 401 | int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 402 | int s = ((lane & 1) ? |
| 403 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : |
| 404 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); |
| 405 | u8 l = edp_link_status(link_status, i); |
| 406 | |
| 407 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
| 408 | } |
| 409 | |
| 410 | static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status, |
| 411 | int lane) |
| 412 | { |
| 413 | int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 414 | int s = ((lane & 1) ? |
| 415 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : |
| 416 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); |
| 417 | u8 l = edp_link_status(link_status, i); |
| 418 | |
| 419 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
| 420 | } |
| 421 | |
| 422 | static void edp_get_adjust_train(const u8 *link_status, int lane_count, |
| 423 | u8 train_set[]) |
| 424 | { |
| 425 | uint v = 0; |
| 426 | uint p = 0; |
| 427 | int lane; |
| 428 | |
| 429 | for (lane = 0; lane < lane_count; lane++) { |
| 430 | uint this_v, this_p; |
| 431 | |
| 432 | this_v = rk_edp_get_adjust_request_voltage(link_status, lane); |
| 433 | this_p = rk_edp_get_adjust_request_pre_emphasis(link_status, |
| 434 | lane); |
| 435 | |
| 436 | debug("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
| 437 | lane, |
| 438 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
| 439 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
| 440 | |
| 441 | if (this_v > v) |
| 442 | v = this_v; |
| 443 | if (this_p > p) |
| 444 | p = this_p; |
| 445 | } |
| 446 | |
| 447 | if (v >= DP_VOLTAGE_MAX) |
| 448 | v |= DP_TRAIN_MAX_SWING_REACHED; |
| 449 | |
| 450 | if (p >= DP_PRE_EMPHASIS_MAX) |
| 451 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 452 | |
| 453 | debug("using signal parameters: voltage %s pre_emph %s\n", |
| 454 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) |
| 455 | >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
| 456 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) |
| 457 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
| 458 | |
| 459 | for (lane = 0; lane < 4; lane++) |
| 460 | train_set[lane] = v | p; |
| 461 | } |
| 462 | |
| 463 | static int rk_edp_link_train_cr(struct rk_edp_priv *edp) |
| 464 | { |
| 465 | struct rk3288_edp *regs = edp->regs; |
| 466 | int clock_recovery; |
| 467 | uint voltage, tries = 0; |
| 468 | u8 status[DP_LINK_STATUS_SIZE]; |
| 469 | int i, ret; |
| 470 | u8 value; |
| 471 | |
| 472 | value = DP_TRAINING_PATTERN_1; |
| 473 | writel(value, ®s->dp_training_ptn_set); |
| 474 | ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1); |
| 475 | if (ret) |
| 476 | return ret; |
| 477 | memset(edp->train_set, '\0', sizeof(edp->train_set)); |
| 478 | |
| 479 | /* clock recovery loop */ |
| 480 | clock_recovery = 0; |
| 481 | tries = 0; |
| 482 | voltage = 0xff; |
| 483 | |
| 484 | while (1) { |
| 485 | rk_edp_set_link_training(edp, edp->train_set); |
| 486 | ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET, |
| 487 | edp->train_set, |
| 488 | edp->link_train.lane_count); |
| 489 | if (ret) |
| 490 | return ret; |
| 491 | |
| 492 | mdelay(1); |
| 493 | |
| 494 | ret = rk_edp_dpcd_read_link_status(edp, status); |
| 495 | if (ret) { |
| 496 | printf("displayport link status failed, ret=%d\n", ret); |
| 497 | break; |
| 498 | } |
| 499 | |
| 500 | clock_recovery = rk_edp_clock_recovery(status, |
| 501 | edp->link_train.lane_count); |
| 502 | if (!clock_recovery) |
| 503 | break; |
| 504 | |
| 505 | for (i = 0; i < edp->link_train.lane_count; i++) { |
| 506 | if ((edp->train_set[i] & |
| 507 | DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 508 | break; |
| 509 | } |
| 510 | if (i == edp->link_train.lane_count) { |
| 511 | printf("clock recovery reached max voltage\n"); |
| 512 | break; |
| 513 | } |
| 514 | |
| 515 | if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == |
| 516 | voltage) { |
| 517 | if (++tries == MAX_CR_LOOP) { |
| 518 | printf("clock recovery tried 5 times\n"); |
| 519 | break; |
| 520 | } |
| 521 | } else { |
| 522 | tries = 0; |
| 523 | } |
| 524 | |
| 525 | voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 526 | |
| 527 | /* Compute new train_set as requested by sink */ |
| 528 | edp_get_adjust_train(status, edp->link_train.lane_count, |
| 529 | edp->train_set); |
| 530 | } |
| 531 | if (clock_recovery) { |
| 532 | printf("clock recovery failed: %d\n", clock_recovery); |
| 533 | return clock_recovery; |
| 534 | } else { |
| 535 | debug("clock recovery at voltage %d pre-emphasis %d\n", |
| 536 | edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
| 537 | (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 538 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 539 | return 0; |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | static int rk_edp_link_train_ce(struct rk_edp_priv *edp) |
| 544 | { |
| 545 | struct rk3288_edp *regs = edp->regs; |
| 546 | int channel_eq; |
| 547 | u8 value; |
| 548 | int tries; |
| 549 | u8 status[DP_LINK_STATUS_SIZE]; |
| 550 | int ret; |
| 551 | |
| 552 | value = DP_TRAINING_PATTERN_2; |
| 553 | writel(value, ®s->dp_training_ptn_set); |
| 554 | ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1); |
| 555 | if (ret) |
| 556 | return ret; |
| 557 | |
| 558 | /* channel equalization loop */ |
| 559 | channel_eq = 0; |
| 560 | for (tries = 0; tries < 5; tries++) { |
| 561 | rk_edp_set_link_training(edp, edp->train_set); |
| 562 | udelay(400); |
| 563 | |
| 564 | if (rk_edp_dpcd_read_link_status(edp, status) < 0) { |
| 565 | printf("displayport link status failed\n"); |
| 566 | return -1; |
| 567 | } |
| 568 | |
| 569 | channel_eq = rk_edp_channel_eq(status, |
| 570 | edp->link_train.lane_count); |
| 571 | if (!channel_eq) |
| 572 | break; |
| 573 | edp_get_adjust_train(status, edp->link_train.lane_count, |
| 574 | edp->train_set); |
| 575 | } |
| 576 | |
| 577 | if (channel_eq) { |
| 578 | printf("channel eq failed, ret=%d\n", channel_eq); |
| 579 | return channel_eq; |
| 580 | } |
| 581 | |
| 582 | debug("channel eq at voltage %d pre-emphasis %d\n", |
| 583 | edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
| 584 | (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
| 585 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 586 | |
| 587 | return 0; |
| 588 | } |
| 589 | |
| 590 | static int rk_edp_init_training(struct rk_edp_priv *edp) |
| 591 | { |
| 592 | u8 values[3]; |
| 593 | int ret; |
| 594 | |
| 595 | ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values, |
| 596 | sizeof(values)); |
| 597 | if (ret < 0) |
| 598 | return ret; |
| 599 | |
| 600 | edp->link_train.revision = values[0]; |
| 601 | edp->link_train.link_rate = values[1]; |
| 602 | edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK; |
| 603 | |
| 604 | debug("max link rate:%d.%dGps max number of lanes:%d\n", |
| 605 | edp->link_train.link_rate * 27 / 100, |
| 606 | edp->link_train.link_rate * 27 % 100, |
| 607 | edp->link_train.lane_count); |
| 608 | |
| 609 | if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) && |
| 610 | (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) { |
| 611 | debug("Rx Max Link Rate is abnormal :%x\n", |
| 612 | edp->link_train.link_rate); |
| 613 | return -EPERM; |
| 614 | } |
| 615 | |
| 616 | if (edp->link_train.lane_count == 0) { |
| 617 | debug("Rx Max Lane count is abnormal :%x\n", |
| 618 | edp->link_train.lane_count); |
| 619 | return -EPERM; |
| 620 | } |
| 621 | |
| 622 | ret = rk_edp_link_power_up(edp); |
| 623 | if (ret) |
| 624 | return ret; |
| 625 | |
| 626 | return rk_edp_link_configure(edp); |
| 627 | } |
| 628 | |
| 629 | static int rk_edp_hw_link_training(struct rk_edp_priv *edp) |
| 630 | { |
| 631 | ulong start; |
| 632 | u32 val; |
| 633 | int ret; |
| 634 | |
| 635 | /* Set link rate and count as you want to establish */ |
| 636 | writel(edp->link_train.link_rate, &edp->regs->link_bw_set); |
| 637 | writel(edp->link_train.lane_count, &edp->regs->lane_count_set); |
| 638 | |
| 639 | ret = rk_edp_link_train_cr(edp); |
| 640 | if (ret) |
| 641 | return ret; |
| 642 | ret = rk_edp_link_train_ce(edp); |
| 643 | if (ret) |
| 644 | return ret; |
| 645 | |
| 646 | writel(HW_LT_EN, &edp->regs->dp_hw_link_training); |
| 647 | start = get_timer(0); |
| 648 | do { |
| 649 | val = readl(&edp->regs->dp_hw_link_training); |
| 650 | if (!(val & HW_LT_EN)) |
| 651 | break; |
| 652 | } while (get_timer(start) < 10); |
| 653 | |
| 654 | if (val & HW_LT_ERR_CODE_MASK) { |
| 655 | printf("edp hw link training error: %d\n", |
| 656 | val >> HW_LT_ERR_CODE_SHIFT); |
| 657 | return -EIO; |
| 658 | } |
| 659 | |
| 660 | return 0; |
| 661 | } |
| 662 | |
| 663 | static int rk_edp_select_i2c_device(struct rk3288_edp *regs, |
| 664 | unsigned int device_addr, |
| 665 | unsigned int val_addr) |
| 666 | { |
| 667 | int ret; |
| 668 | |
| 669 | /* Set EDID device address */ |
| 670 | writel(device_addr, ®s->aux_addr_7_0); |
| 671 | writel(0x0, ®s->aux_addr_15_8); |
| 672 | writel(0x0, ®s->aux_addr_19_16); |
| 673 | |
| 674 | /* Set offset from base address of EDID device */ |
| 675 | writel(val_addr, ®s->buf_data[0]); |
| 676 | |
| 677 | /* |
| 678 | * Set I2C transaction and write address |
| 679 | * If bit 3 is 1, DisplayPort transaction. |
| 680 | * If Bit 3 is 0, I2C transaction. |
| 681 | */ |
| 682 | writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | |
| 683 | AUX_TX_COMM_WRITE, ®s->aux_ch_ctl_1); |
| 684 | |
| 685 | /* Start AUX transaction */ |
| 686 | ret = rk_edp_start_aux_transaction(regs); |
| 687 | if (ret != 0) { |
| 688 | debug("select_i2c_device Aux Transaction fail!\n"); |
| 689 | return ret; |
| 690 | } |
| 691 | |
| 692 | return 0; |
| 693 | } |
| 694 | |
| 695 | static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr, |
| 696 | unsigned int val_addr, unsigned int count, u8 edid[]) |
| 697 | { |
| 698 | u32 val; |
| 699 | unsigned int i, j; |
| 700 | unsigned int cur_data_idx; |
| 701 | unsigned int defer = 0; |
| 702 | int ret = 0; |
| 703 | |
| 704 | for (i = 0; i < count; i += 16) { |
| 705 | for (j = 0; j < 10; j++) { /* try 10 times */ |
| 706 | /* Clear AUX CH data buffer */ |
| 707 | writel(BUF_CLR, ®s->buf_data_ctl); |
| 708 | |
| 709 | /* Set normal AUX CH command */ |
| 710 | clrbits_le32(®s->aux_ch_ctl_2, ADDR_ONLY); |
| 711 | |
| 712 | /* |
| 713 | * If Rx sends defer, Tx sends only reads |
| 714 | * request without sending addres |
| 715 | */ |
| 716 | if (!defer) { |
| 717 | ret = rk_edp_select_i2c_device(regs, |
| 718 | device_addr, |
| 719 | val_addr + i); |
| 720 | } else { |
| 721 | defer = 0; |
| 722 | } |
| 723 | |
| 724 | /* |
| 725 | * Set I2C transaction and write data |
| 726 | * If bit 3 is 1, DisplayPort transaction. |
| 727 | * If Bit 3 is 0, I2C transaction. |
| 728 | */ |
| 729 | writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION | |
| 730 | AUX_TX_COMM_READ, ®s->aux_ch_ctl_1); |
| 731 | |
| 732 | /* Start AUX transaction */ |
| 733 | ret = rk_edp_start_aux_transaction(regs); |
| 734 | if (ret == 0) { |
| 735 | break; |
| 736 | } else { |
| 737 | debug("Aux Transaction fail!\n"); |
| 738 | continue; |
| 739 | } |
| 740 | |
| 741 | /* Check if Rx sends defer */ |
| 742 | val = readl(®s->aux_rx_comm); |
| 743 | if (val == AUX_RX_COMM_AUX_DEFER || |
| 744 | val == AUX_RX_COMM_I2C_DEFER) { |
| 745 | debug("Defer: %d\n\n", val); |
| 746 | defer = 1; |
| 747 | } |
| 748 | } |
| 749 | |
| 750 | if (ret) |
| 751 | return ret; |
| 752 | |
| 753 | for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { |
| 754 | val = readl(®s->buf_data[cur_data_idx]); |
| 755 | edid[i + cur_data_idx] = (u8)val; |
| 756 | } |
| 757 | } |
| 758 | |
| 759 | return 0; |
| 760 | } |
| 761 | |
| 762 | static int rk_edp_set_link_train(struct rk_edp_priv *edp) |
| 763 | { |
| 764 | int ret; |
| 765 | |
| 766 | ret = rk_edp_init_training(edp); |
| 767 | if (ret) { |
| 768 | printf("DP LT init failed!\n"); |
| 769 | return ret; |
| 770 | } |
| 771 | |
| 772 | ret = rk_edp_hw_link_training(edp); |
| 773 | if (ret) |
| 774 | return ret; |
| 775 | |
| 776 | return 0; |
| 777 | } |
| 778 | |
| 779 | static void rk_edp_init_video(struct rk3288_edp *regs) |
| 780 | { |
| 781 | writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG, |
| 782 | ®s->common_int_sta_1); |
| 783 | writel(CHA_CRI(4) | CHA_CTRL, ®s->sys_ctl_2); |
| 784 | writel(VID_HRES_TH(2) | VID_VRES_TH(0), ®s->video_ctl_8); |
| 785 | } |
| 786 | |
| 787 | static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs) |
| 788 | { |
| 789 | clrbits_le32(®s->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N); |
| 790 | } |
| 791 | |
| 792 | static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs, |
| 793 | enum clock_recovery_m_value_type type, |
| 794 | u32 m_value, |
| 795 | u32 n_value) |
| 796 | { |
| 797 | if (type == REGISTER_M) { |
| 798 | setbits_le32(®s->sys_ctl_4, FIX_M_VID); |
| 799 | writel(m_value & 0xff, ®s->m_vid_0); |
| 800 | writel((m_value >> 8) & 0xff, ®s->m_vid_1); |
| 801 | writel((m_value >> 16) & 0xff, ®s->m_vid_2); |
| 802 | |
| 803 | writel(n_value & 0xf, ®s->n_vid_0); |
| 804 | writel((n_value >> 8) & 0xff, ®s->n_vid_1); |
| 805 | writel((n_value >> 16) & 0xff, ®s->n_vid_2); |
| 806 | } else { |
| 807 | clrbits_le32(®s->sys_ctl_4, FIX_M_VID); |
| 808 | |
| 809 | writel(0x00, ®s->n_vid_0); |
| 810 | writel(0x80, ®s->n_vid_1); |
| 811 | writel(0x00, ®s->n_vid_2); |
| 812 | } |
| 813 | } |
| 814 | |
| 815 | static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs) |
| 816 | { |
| 817 | ulong start; |
| 818 | u32 val; |
| 819 | |
| 820 | start = get_timer(0); |
| 821 | do { |
| 822 | val = readl(®s->sys_ctl_1); |
| 823 | |
| 824 | /* must write value to update DET_STA bit status */ |
| 825 | writel(val, ®s->sys_ctl_1); |
| 826 | val = readl(®s->sys_ctl_1); |
| 827 | if (!(val & DET_STA)) |
| 828 | continue; |
| 829 | |
| 830 | val = readl(®s->sys_ctl_2); |
| 831 | |
| 832 | /* must write value to update CHA_STA bit status */ |
| 833 | writel(val, ®s->sys_ctl_2); |
| 834 | val = readl(®s->sys_ctl_2); |
| 835 | if (!(val & CHA_STA)) |
| 836 | return 0; |
| 837 | |
| 838 | } while (get_timer(start) < 100); |
| 839 | |
| 840 | return -ETIMEDOUT; |
| 841 | } |
| 842 | |
| 843 | static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp) |
| 844 | { |
| 845 | ulong start; |
| 846 | u32 val; |
| 847 | |
| 848 | start = get_timer(0); |
| 849 | do { |
| 850 | val = readl(&edp->regs->sys_ctl_3); |
| 851 | |
| 852 | /* must write value to update STRM_VALID bit status */ |
| 853 | writel(val, &edp->regs->sys_ctl_3); |
| 854 | |
| 855 | val = readl(&edp->regs->sys_ctl_3); |
| 856 | if (!(val & STRM_VALID)) |
| 857 | return 0; |
| 858 | } while (get_timer(start) < 100); |
| 859 | |
| 860 | return -ETIMEDOUT; |
| 861 | } |
| 862 | |
| 863 | static int rk_edp_config_video(struct rk_edp_priv *edp) |
| 864 | { |
| 865 | int ret; |
| 866 | |
| 867 | rk_edp_config_video_slave_mode(edp->regs); |
| 868 | |
| 869 | if (!rk_edp_get_pll_locked(edp->regs)) { |
| 870 | debug("PLL is not locked yet.\n"); |
| 871 | return -ETIMEDOUT; |
| 872 | } |
| 873 | |
| 874 | ret = rk_edp_is_video_stream_clock_on(edp->regs); |
| 875 | if (ret) |
| 876 | return ret; |
| 877 | |
| 878 | /* Set to use the register calculated M/N video */ |
| 879 | rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0); |
| 880 | |
| 881 | /* For video bist, Video timing must be generated by register */ |
| 882 | clrbits_le32(&edp->regs->video_ctl_10, F_SEL); |
| 883 | |
| 884 | /* Disable video mute */ |
| 885 | clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); |
| 886 | |
| 887 | /* Enable video at next frame */ |
| 888 | setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN); |
| 889 | |
| 890 | return rk_edp_is_video_stream_on(edp); |
| 891 | } |
| 892 | |
| 893 | static void rockchip_edp_force_hpd(struct rk_edp_priv *edp) |
| 894 | { |
| 895 | setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL); |
| 896 | } |
| 897 | |
| 898 | static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp) |
| 899 | { |
| 900 | u32 val; |
| 901 | |
| 902 | val = readl(&edp->regs->sys_ctl_3); |
| 903 | if (val & HPD_STATUS) |
| 904 | return 1; |
| 905 | |
| 906 | return 0; |
| 907 | } |
| 908 | |
| 909 | /* |
| 910 | * support edp HPD function |
| 911 | * some hardware version do not support edp hdp, |
| 912 | * we use 200ms to try to get the hpd single now, |
| 913 | * if we can not get edp hpd single, it will delay 200ms, |
| 914 | * also meet the edp power timing request, to compatible |
| 915 | * all of the hardware version |
| 916 | */ |
| 917 | static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp) |
| 918 | { |
| 919 | ulong start; |
| 920 | |
| 921 | start = get_timer(0); |
| 922 | do { |
| 923 | if (rockchip_edp_get_plug_in_status(edp)) |
| 924 | return; |
| 925 | udelay(100); |
| 926 | } while (get_timer(start) < 200); |
| 927 | |
| 928 | debug("do not get hpd single, force hpd\n"); |
| 929 | rockchip_edp_force_hpd(edp); |
| 930 | } |
| 931 | |
| 932 | static int rk_edp_enable(struct udevice *dev, int panel_bpp, |
| 933 | const struct display_timing *edid) |
| 934 | { |
| 935 | struct rk_edp_priv *priv = dev_get_priv(dev); |
| 936 | int ret = 0; |
| 937 | |
| 938 | ret = rk_edp_set_link_train(priv); |
| 939 | if (ret) { |
| 940 | printf("link train failed!\n"); |
| 941 | return ret; |
| 942 | } |
| 943 | |
| 944 | rk_edp_init_video(priv->regs); |
| 945 | ret = rk_edp_config_video(priv); |
| 946 | if (ret) { |
| 947 | printf("config video failed\n"); |
| 948 | return ret; |
| 949 | } |
| 950 | ret = panel_enable_backlight(priv->panel); |
| 951 | if (ret) { |
| 952 | debug("%s: backlight error: %d\n", __func__, ret); |
| 953 | return ret; |
| 954 | } |
| 955 | |
| 956 | return 0; |
| 957 | } |
| 958 | |
| 959 | static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size) |
| 960 | { |
| 961 | struct rk_edp_priv *priv = dev_get_priv(dev); |
| 962 | u32 edid_size = EDID_LENGTH; |
| 963 | int ret; |
| 964 | int i; |
| 965 | |
| 966 | for (i = 0; i < 3; i++) { |
| 967 | ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER, |
| 968 | EDID_LENGTH, &buf[EDID_HEADER]); |
| 969 | if (ret) { |
| 970 | debug("EDID read failed\n"); |
| 971 | continue; |
| 972 | } |
| 973 | |
| 974 | /* |
| 975 | * check if the EDID has an extension flag, and read additional |
| 976 | * EDID data if needed |
| 977 | */ |
| 978 | if (buf[EDID_EXTENSION_FLAG]) { |
| 979 | edid_size += EDID_LENGTH; |
| 980 | ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, |
| 981 | EDID_LENGTH, EDID_LENGTH, |
| 982 | &buf[EDID_LENGTH]); |
| 983 | if (ret) { |
| 984 | debug("EDID Read failed!\n"); |
| 985 | continue; |
| 986 | } |
| 987 | } |
| 988 | goto done; |
| 989 | } |
| 990 | |
| 991 | /* After 3 attempts, give up */ |
| 992 | return ret; |
| 993 | |
| 994 | done: |
| 995 | return edid_size; |
| 996 | } |
| 997 | |
| 998 | static int rk_edp_ofdata_to_platdata(struct udevice *dev) |
| 999 | { |
| 1000 | struct rk_edp_priv *priv = dev_get_priv(dev); |
| 1001 | |
Kever Yang | e686739 | 2020-02-19 09:45:38 +0800 | [diff] [blame] | 1002 | priv->regs = dev_read_addr_ptr(dev); |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 1003 | priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
| 1004 | |
| 1005 | return 0; |
| 1006 | } |
| 1007 | |
Simon Glass | c4bd91f | 2017-05-31 17:57:28 -0600 | [diff] [blame] | 1008 | static int rk_edp_remove(struct udevice *dev) |
| 1009 | { |
| 1010 | struct rk_edp_priv *priv = dev_get_priv(dev); |
| 1011 | struct rk3288_edp *regs = priv->regs; |
| 1012 | |
| 1013 | setbits_le32(®s->video_ctl_1, VIDEO_MUTE); |
| 1014 | clrbits_le32(®s->video_ctl_1, VIDEO_EN); |
| 1015 | clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL); |
| 1016 | setbits_le32(®s->func_en_1, SW_FUNC_EN_N); |
| 1017 | |
| 1018 | return 0; |
| 1019 | } |
| 1020 | |
| 1021 | static int rk_edp_probe(struct udevice *dev) |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 1022 | { |
| 1023 | struct display_plat *uc_plat = dev_get_uclass_platdata(dev); |
| 1024 | struct rk_edp_priv *priv = dev_get_priv(dev); |
| 1025 | struct rk3288_edp *regs = priv->regs; |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 1026 | struct clk clk; |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 1027 | int ret; |
| 1028 | |
| 1029 | ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel", |
| 1030 | &priv->panel); |
| 1031 | if (ret) { |
| 1032 | debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__, |
| 1033 | dev->name, ret); |
| 1034 | return ret; |
| 1035 | } |
| 1036 | |
| 1037 | int vop_id = uc_plat->source_id; |
| 1038 | debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id); |
| 1039 | |
| 1040 | ret = clk_get_by_index(dev, 1, &clk); |
| 1041 | if (ret >= 0) { |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 1042 | ret = clk_set_rate(&clk, 0); |
| 1043 | clk_free(&clk); |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 1044 | } |
| 1045 | if (ret) { |
| 1046 | debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret); |
| 1047 | return ret; |
| 1048 | } |
| 1049 | |
| 1050 | ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); |
| 1051 | if (ret >= 0) { |
Stephen Warren | a962243 | 2016-06-17 09:44:00 -0600 | [diff] [blame] | 1052 | ret = clk_set_rate(&clk, 192000000); |
| 1053 | clk_free(&clk); |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 1054 | } |
| 1055 | if (ret < 0) { |
| 1056 | debug("%s: Failed to set clock in source device '%s': ret=%d\n", |
| 1057 | __func__, uc_plat->src_dev->name, ret); |
| 1058 | return ret; |
| 1059 | } |
| 1060 | |
| 1061 | /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */ |
| 1062 | rk_setreg(&priv->grf->soc_con12, 1 << 4); |
| 1063 | |
| 1064 | /* select epd signal from vop0 or vop1 */ |
Patrick Wildt | 54fe2bd | 2020-06-07 20:36:12 +0200 | [diff] [blame] | 1065 | rk_clrsetreg(&priv->grf->soc_con6, (1 << 5), |
| 1066 | (vop_id == 1) ? (1 << 5) : (0 << 5)); |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 1067 | |
| 1068 | rockchip_edp_wait_hpd(priv); |
| 1069 | |
| 1070 | rk_edp_init_refclk(regs); |
| 1071 | rk_edp_init_interrupt(regs); |
| 1072 | rk_edp_enable_sw_function(regs); |
| 1073 | ret = rk_edp_init_analog_func(regs); |
| 1074 | if (ret) |
| 1075 | return ret; |
| 1076 | rk_edp_init_aux(regs); |
| 1077 | |
| 1078 | return 0; |
| 1079 | } |
| 1080 | |
| 1081 | static const struct dm_display_ops dp_rockchip_ops = { |
| 1082 | .read_edid = rk_edp_read_edid, |
| 1083 | .enable = rk_edp_enable, |
| 1084 | }; |
| 1085 | |
| 1086 | static const struct udevice_id rockchip_dp_ids[] = { |
| 1087 | { .compatible = "rockchip,rk3288-edp" }, |
| 1088 | { } |
| 1089 | }; |
| 1090 | |
| 1091 | U_BOOT_DRIVER(dp_rockchip) = { |
| 1092 | .name = "edp_rockchip", |
| 1093 | .id = UCLASS_DISPLAY, |
| 1094 | .of_match = rockchip_dp_ids, |
| 1095 | .ops = &dp_rockchip_ops, |
| 1096 | .ofdata_to_platdata = rk_edp_ofdata_to_platdata, |
| 1097 | .probe = rk_edp_probe, |
Simon Glass | c4bd91f | 2017-05-31 17:57:28 -0600 | [diff] [blame] | 1098 | .remove = rk_edp_remove, |
Simon Glass | 9160b4c | 2016-01-21 19:45:04 -0700 | [diff] [blame] | 1099 | .priv_auto_alloc_size = sizeof(struct rk_edp_priv), |
| 1100 | }; |