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git01.mediatek.com / filogic / uboot / ff184fe9ab195cd9fdb7d72774872bfdbf8669c1 / . / drivers / reset / Kconfig
blob: 3fdfe4a6cb070d1fa6898edb20ee4726ccf65659 [file] [log] [blame]
Stephen Warren185ad872016-06-17 09:43:58 -0600[diff] [blame]1menu "Reset Controller Support"
2
3config DM_RESET
4 bool "Enable reset controllers using Driver Model"
5 depends on DM && OF_CONTROL
6 help
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
11 cases this API is applicable to chips outside the CPU as well,
12 although driving such reset isgnals using GPIOs may be more
13 appropriate in this case.
14
Stephen Warren6488e642016-06-17 09:43:59 -0600[diff] [blame]15config SANDBOX_RESET
16 bool "Enable the sandbox reset test driver"
17 depends on DM_MAILBOX && SANDBOX
18 help
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
21 doing anything beyond a little error checking.
22
Patrice Chotard1235aa02017-03-22 10:54:03 +0100[diff] [blame]23config STI_RESET
24 bool "Enable the STi reset"
25 depends on ARCH_STI
26 help
27 Support for reset controllers on STMicroelectronics STiH407 family SoCs.
28 Say Y if you want to control reset signals provided by system config
29 block.
30
Patrice Chotard5c121e12017-09-13 18:00:07 +0200[diff] [blame]31config STM32_RESET
32 bool "Enable the STM32 reset"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400[diff] [blame]33 depends on ARCH_STM32 || ARCH_STM32MP
Patrice Chotard5c121e12017-09-13 18:00:07 +0200[diff] [blame]34 help
35 Support for reset controllers on STMicroelectronics STM32 family SoCs.
Trevor Woernere3d9c992020-05-06 08:02:43 -0400[diff] [blame]36 This reset driver is compatible with STM32 F4/F7 and H7 SoCs.
Patrice Chotard5c121e12017-09-13 18:00:07 +0200[diff] [blame]37
Stephen Warren3017ab52016-09-13 10:45:58 -0600[diff] [blame]38config TEGRA_CAR_RESET
39 bool "Enable Tegra CAR-based reset driver"
40 depends on TEGRA_CAR
41 help
42 Enable support for manipulating Tegra's on-SoC reset signals via
43 direct register access to the Tegra CAR (Clock And Reset controller).
44
Stephen Warrenfccc9c52016-08-08 11:28:25 -0600[diff] [blame]45config TEGRA186_RESET
46 bool "Enable Tegra186 BPMP-based reset driver"
47 depends on TEGRA186_BPMP
48 help
49 Enable support for manipulating Tegra's on-SoC reset signals via IPC
50 requests to the BPMP (Boot and Power Management Processor).
51
Andreas Dannenberg4cfdf4d2018-08-27 15:57:41 +0530[diff] [blame]52config RESET_TI_SCI
53 bool "TI System Control Interface (TI SCI) reset driver"
54 depends on DM_RESET && TI_SCI_PROTOCOL
55 help
56 This enables the reset driver support over TI System Control Interface
57 available on some new TI's SoCs. If you wish to use reset resources
58 managed by the TI System Controller, say Y here. Otherwise, say N.
59
Álvaro Fernández Rojas5161bd32017-05-03 15:10:21 +0200[diff] [blame]60config RESET_BCM6345
61 bool "Reset controller driver for BCM6345"
62 depends on DM_RESET && ARCH_BMIPS
63 help
64 Support reset controller on BCM6345.
65
Masahiro Yamada2aa4b5b2016-10-08 13:25:31 +0900[diff] [blame]66config RESET_UNIPHIER
67 bool "Reset controller driver for UniPhier SoCs"
68 depends on ARCH_UNIPHIER
69 default y
70 help
71 Support for reset controllers on UniPhier SoCs.
72 Say Y if you want to control reset signals provided by System Control
73 block, Media I/O block, Peripheral Block.
74
maxims@google.com750875c2017-04-17 12:00:24 -0700[diff] [blame]75config AST2500_RESET
76 bool "Reset controller driver for AST2500 SoCs"
77 depends on DM_RESET && WDT_ASPEED
78 default y if ASPEED_AST2500
79 help
80 Support for reset controller on AST2500 SoC. This controller uses
81 watchdog to reset different peripherals and thus only supports
82 resets that are supported by watchdog. The main limitation though
83 is that some reset signals, like I2C or MISC reset multiple devices.
84
Elaine Zhang6e9a3a72017-12-19 18:22:37 +0800[diff] [blame]85config RESET_ROCKCHIP
86 bool "Reset controller driver for Rockchip SoCs"
87 depends on DM_RESET && ARCH_ROCKCHIP && CLK
88 default y
89 help
90 Support for reset controller on rockchip SoC. The main limitation
91 though is that some reset signals, like I2C or MISC reset multiple
92 devices.
93
Eugeniy Paltsev062da422019-10-08 19:29:30 +0300[diff] [blame]94config RESET_HSDK
95 bool "Synopsys HSDK Reset Driver"
96 depends on DM_RESET && TARGET_HSDK
97 default y
98 help
99 This enables the reset controller driver for HSDK board.
100
Neil Armstrong4f03d6b2018-03-29 14:55:25 +0200[diff] [blame]101config RESET_MESON
102 bool "Reset controller driver for Amlogic Meson SoCs"
103 depends on DM_RESET && ARCH_MESON
104 imply REGMAP
105 default y
106 help
107 Support for reset controller on Amlogic Meson SoC.
108
Dinh Nguyen5427f5a2018-04-04 17:18:20 -0500[diff] [blame]109config RESET_SOCFPGA
110 bool "Reset controller driver for SoCFPGA"
111 depends on DM_RESET && ARCH_SOCFPGA
112 default y
113 help
114 Support for reset controller on SoCFPGA platform.
115
developerd48dd9a2018-12-20 16:12:51 +0800[diff] [blame]116config RESET_MEDIATEK
117 bool "Reset controller driver for MediaTek SoCs"
118 depends on DM_RESET && ARCH_MEDIATEK && CLK
119 default y
120 help
121 Support for reset controller on MediaTek SoCs.
122
developer074393a2019-09-25 17:45:29 +0800[diff] [blame]123config RESET_MTMIPS
124 bool "Reset controller driver for MediaTek MIPS platform"
125 depends on DM_RESET && ARCH_MTMIPS
126 default y
127 help
128 Support for reset controller on MediaTek MIPS platform.
129
Jagan Teki7f6c2a82019-01-18 22:18:13 +0530[diff] [blame]130config RESET_SUNXI
131 bool "RESET support for Allwinner SoCs"
132 depends on DM_RESET && ARCH_SUNXI
133 default y
134 help
135 This enables support for common reset driver for
136 Allwinner SoCs.
137
Shawn Guo8aa8f302019-03-20 15:32:39 +0800[diff] [blame]138config RESET_HISILICON
139 bool "Reset controller driver for HiSilicon SoCs"
140 depends on DM_RESET
141 help
142 Support for reset controller on HiSilicon SoCs.
143
Patrick Wildtdbc644f2019-10-03 16:08:35 +0200[diff] [blame]144config RESET_IMX7
145 bool "i.MX7/8 Reset Driver"
146 depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M)
147 default y
148 help
149 Support for reset controller on i.MX7/8 SoCs.
150
Robert Markof5edc7a2020-09-10 16:00:02 +0200[diff] [blame]151config RESET_IPQ419
152 bool "Reset driver for Qualcomm IPQ40xx SoCs"
153 depends on DM_RESET && ARCH_IPQ40XX
154 default y
155 help
156 Support for reset controller on Qualcomm
157 IPQ40xx SoCs.
158
Sagar Shrikant Kadam2732b2d2020-07-29 02:36:14 -0700[diff] [blame]159config RESET_SIFIVE
160 bool "Reset Driver for SiFive SoC's"
161 depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
162 default y
163 help
164 PRCI module within SiFive SoC's provides mechanism to reset
165 different hw blocks like DDR, gemgxl. With this driver we leverage
166 U-Boot's reset framework to reset these hardware blocks.
167
Sean Anderson0c1f6bf2020-06-24 06:41:14 -0400[diff] [blame]168config RESET_SYSCON
169 bool "Enable generic syscon reset driver support"
170 depends on DM_RESET
171 help
172 Support generic syscon mapped register reset devices.
Nicolas Saenz Julienne057bbbd2020-06-29 18:37:23 +0200[diff] [blame]173
174config RESET_RASPBERRYPI
175 bool "Raspberry Pi 4 Firmware Reset Controller Driver"
176 depends on DM_RESET && ARCH_BCM283X
177 default USB_XHCI_PCI
178 help
179 Raspberry Pi 4's co-processor controls some of the board's HW
180 initialization process, but it's up to Linux to trigger it when
181 relevant. This driver provides a reset controller capable of
182 interfacing with RPi4's co-processor and model these firmware
183 initialization routines as reset lines.
Stephen Warren185ad872016-06-17 09:43:58 -0600[diff] [blame]184endmenu