blob: 746071b4150f8c15f9c77d4d8373b3d2e0656792 [file] [log] [blame]
Alifer Moraesa0a29482020-03-06 07:46:33 -03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2020 NXP
4 */
5
6#include <common.h>
7#include <env.h>
8#include <init.h>
9#include <malloc.h>
10#include <errno.h>
11#include <asm/io.h>
12#include <miiphy.h>
13#include <netdev.h>
14#include <asm/mach-imx/iomux-v3.h>
15#include <asm-generic/gpio.h>
16#include <fsl_esdhc_imx.h>
17#include <mmc.h>
18#include <asm/arch/imx8mq_pins.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/mach-imx/gpio.h>
21#include <asm/arch/clock.h>
22#include <spl.h>
23
24DECLARE_GLOBAL_DATA_PTR;
25
26#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
27
28#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
29
30static iomux_v3_cfg_t const wdog_pads[] = {
31 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
32};
33
34static iomux_v3_cfg_t const uart_pads[] = {
35 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
36 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
37};
38
39int board_early_init_f(void)
40{
41 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
42
43 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
44 set_wdog_reset(wdog);
45
46 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
47
48 return 0;
49}
50
Alifer Moraesa0a29482020-03-06 07:46:33 -030051#ifdef CONFIG_FEC_MXC
52static int setup_fec(void)
53{
54 struct iomuxc_gpr_base_regs *gpr =
55 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
56
57 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
58 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
59 return set_clk_enet(ENET_125MHZ);
60}
61
62int board_phy_config(struct phy_device *phydev)
63{
64 /* enable rgmii rxc skew and phy mode select to RGMII copper */
65 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
66 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
67
68 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
69 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
70
71 if (phydev->drv->config)
72 phydev->drv->config(phydev);
73 return 0;
74}
75#endif
76
77int board_init(void)
78{
79#ifdef CONFIG_FEC_MXC
80 setup_fec();
81#endif
82
83 return 0;
84}
85
86int board_mmc_get_env_dev(int devno)
87{
88 return devno;
89}