wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
wdenk | 8d5d28a | 2005-04-02 22:37:54 +0000 | [diff] [blame] | 2 | * (C) Copyright 2001-2005 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* ------------------------------------------------------------------------- */ |
| 9 | |
| 10 | /* |
| 11 | * board/config.h - configuration options, board specific |
| 12 | */ |
| 13 | |
| 14 | #ifndef __CONFIG_H |
| 15 | #define __CONFIG_H |
| 16 | |
| 17 | /* |
| 18 | * High Level Configuration Options |
| 19 | * (easy to change) |
| 20 | */ |
| 21 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 22 | #define CONFIG_MPC8245 1 |
| 23 | #define CONFIG_SANDPOINT 1 |
| 24 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 25 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
Wolfgang Denk | 79362d3 | 2010-11-23 23:48:56 +0100 | [diff] [blame] | 26 | #define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds" |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 27 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 28 | #if 0 |
| 29 | #define USE_DINK32 1 |
| 30 | #else |
| 31 | #undef USE_DINK32 |
| 32 | #endif |
| 33 | |
| 34 | #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ |
| 35 | #define CONFIG_BAUDRATE 9600 |
| 36 | #define CONFIG_DRAM_SPEED 100 /* MHz */ |
| 37 | |
wdenk | 8d5d28a | 2005-04-02 22:37:54 +0000 | [diff] [blame] | 38 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
| 39 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 40 | |
Jon Loeliger | d866df3 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 41 | /* |
Jon Loeliger | beb9ff4 | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 42 | * BOOTP options |
| 43 | */ |
| 44 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 45 | #define CONFIG_BOOTP_BOOTPATH |
| 46 | #define CONFIG_BOOTP_GATEWAY |
| 47 | #define CONFIG_BOOTP_HOSTNAME |
| 48 | |
| 49 | |
| 50 | /* |
Jon Loeliger | d866df3 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 51 | * Command line configuration. |
| 52 | */ |
| 53 | #include <config_cmd_default.h> |
| 54 | |
| 55 | #define CONFIG_CMD_DHCP |
| 56 | #define CONFIG_CMD_ELF |
| 57 | #define CONFIG_CMD_I2C |
| 58 | #define CONFIG_CMD_EEPROM |
| 59 | #define CONFIG_CMD_NFS |
| 60 | #define CONFIG_CMD_PCI |
| 61 | #define CONFIG_CMD_SNTP |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 62 | |
| 63 | |
| 64 | /* |
| 65 | * Miscellaneous configurable options |
| 66 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 69 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 70 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 71 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 72 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 73 | |
| 74 | /*----------------------------------------------------------------------- |
| 75 | * PCI stuff |
| 76 | *----------------------------------------------------------------------- |
| 77 | */ |
| 78 | #define CONFIG_PCI /* include pci support */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 79 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 80 | #undef CONFIG_PCI_PNP |
| 81 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 82 | |
| 83 | #define CONFIG_EEPRO100 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 85 | #define CONFIG_NATSEMI |
| 86 | #define CONFIG_NS8382X |
| 87 | |
| 88 | #define PCI_ENET0_IOADDR 0x80000000 |
| 89 | #define PCI_ENET0_MEMADDR 0x80000000 |
| 90 | #define PCI_ENET1_IOADDR 0x81000000 |
| 91 | #define PCI_ENET1_MEMADDR 0x81000000 |
| 92 | |
| 93 | |
| 94 | /*----------------------------------------------------------------------- |
| 95 | * Start addresses for the final memory configuration |
| 96 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 98 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 100 | #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 101 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 103 | |
| 104 | #if defined (USE_DINK32) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 |
| 106 | #define CONFIG_SYS_MONITOR_BASE 0x00090000 |
| 107 | #define CONFIG_SYS_RAMBOOT 1 |
| 108 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 109 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 112 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | #undef CONFIG_SYS_RAMBOOT |
| 114 | #define CONFIG_SYS_MONITOR_LEN 0x00030000 |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 115 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 116 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 117 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 118 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 120 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 121 | |
| 122 | #endif |
| 123 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 124 | #define CONFIG_SYS_FLASH_BASE 0xFFF00000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 125 | #if 0 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 127 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 128 | #define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 129 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 130 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 131 | #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ |
| 132 | #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 133 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 135 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 137 | #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 138 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | #define CONFIG_SYS_EUMB_ADDR 0xFC000000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 140 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | #define CONFIG_SYS_ISA_MEM 0xFD000000 |
| 142 | #define CONFIG_SYS_ISA_IO 0xFE000000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 143 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 144 | #define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */ |
| 145 | #define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 146 | #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ |
| 147 | #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ |
| 148 | |
| 149 | /* |
| 150 | * select i2c support configuration |
| 151 | * |
| 152 | * Supported configurations are {none, software, hardware} drivers. |
| 153 | * If the software driver is chosen, there are some additional |
| 154 | * configuration items that the driver uses to drive the port pins. |
| 155 | */ |
Heiko Schocher | 479a4cf | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 156 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ |
| 157 | #undef CONFIG_SYS_I2C_SOFT |
| 158 | #define CONFIG_SYS_I2C_SPEED 400000 |
| 159 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 160 | |
Heiko Schocher | 479a4cf | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 161 | #ifdef CONFIG_SYS_I2C_SOFT |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 162 | #error "Soft I2C is not configured properly. Please review!" |
Heiko Schocher | 479a4cf | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 163 | #define CONFIG_SYS_I2C |
| 164 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
| 165 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 166 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
| 167 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) |
| 168 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
| 169 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) |
| 170 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
| 171 | else iop->pdat &= ~0x00010000 |
| 172 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
| 173 | else iop->pdat &= ~0x00020000 |
| 174 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
Heiko Schocher | 479a4cf | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 175 | #endif /* CONFIG_SYS_I2C_SOFT */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 176 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ |
| 178 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
| 179 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 180 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 181 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 182 | #define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 183 | |
| 184 | /*----------------------------------------------------------------------- |
| 185 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 186 | */ |
| 187 | |
| 188 | |
Wolfgang Denk | 4136428 | 2010-11-23 23:17:18 +0100 | [diff] [blame] | 189 | /* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */ |
| 191 | #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */ |
| 192 | #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 193 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 194 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
| 195 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 196 | |
| 197 | /* |
| 198 | * NS87308 Configuration |
| 199 | */ |
Jean-Christophe PLAGNIOL-VILLARD | a44b9aa | 2008-08-13 01:40:40 +0200 | [diff] [blame] | 200 | #define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 201 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 202 | #define CONFIG_SYS_NS87308_BADDR_10 1 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 203 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 204 | #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \ |
| 205 | CONFIG_SYS_NS87308_UART2 | \ |
| 206 | CONFIG_SYS_NS87308_POWRMAN | \ |
| 207 | CONFIG_SYS_NS87308_RTC_APC ) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 208 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #undef CONFIG_SYS_NS87308_PS2MOD |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 210 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | #define CONFIG_SYS_NS87308_CS0_BASE 0x0076 |
| 212 | #define CONFIG_SYS_NS87308_CS0_CONF 0x30 |
| 213 | #define CONFIG_SYS_NS87308_CS1_BASE 0x0075 |
| 214 | #define CONFIG_SYS_NS87308_CS1_CONF 0x30 |
| 215 | #define CONFIG_SYS_NS87308_CS2_BASE 0x0074 |
| 216 | #define CONFIG_SYS_NS87308_CS2_CONF 0x30 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 217 | |
| 218 | /* |
| 219 | * NS16550 Configuration |
| 220 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 221 | #define CONFIG_SYS_NS16550 |
| 222 | #define CONFIG_SYS_NS16550_SERIAL |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 223 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 224 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 225 | |
wdenk | 37bdfdf | 2004-06-10 21:55:33 +0000 | [diff] [blame] | 226 | #if (CONFIG_CONS_INDEX > 2) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 227 | #define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000 |
wdenk | 37bdfdf | 2004-06-10 21:55:33 +0000 | [diff] [blame] | 228 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 229 | #define CONFIG_SYS_NS16550_CLK 1843200 |
wdenk | 37bdfdf | 2004-06-10 21:55:33 +0000 | [diff] [blame] | 230 | #endif |
wdenk | 9e930b6 | 2004-06-19 21:19:10 +0000 | [diff] [blame] | 231 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 232 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE) |
| 233 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE) |
| 234 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500) |
| 235 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 236 | |
| 237 | /* |
| 238 | * Low Level Configuration Settings |
| 239 | * (address mappings, register initial values, etc.) |
| 240 | * You should know what you are doing if you make changes here. |
| 241 | */ |
| 242 | |
| 243 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
| 244 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 245 | #define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */ |
| 246 | #define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 247 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 248 | #define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 249 | |
| 250 | /* the following are for SDRAM only*/ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 251 | #define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */ |
| 252 | #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ |
| 253 | #define CONFIG_SYS_RDLAT 4 /* data latency from read command */ |
| 254 | #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */ |
| 255 | #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ |
| 256 | #define CONFIG_SYS_ACTORW 3 /* Activate to R/W */ |
| 257 | #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ |
| 258 | #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 259 | #if 0 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 260 | #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 261 | #endif |
| 262 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 263 | #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 |
| 264 | #define CONFIG_SYS_EXTROM 1 |
| 265 | #define CONFIG_SYS_REGDIMM 0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 266 | |
| 267 | |
| 268 | /* memory bank settings*/ |
| 269 | /* |
| 270 | * only bits 20-29 are actually used from these vales to set the |
| 271 | * start/end address the upper two bits will be 0, and the lower 20 |
| 272 | * bits will be set to 0x00000 for a start address, or 0xfffff for an |
| 273 | * end address |
| 274 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 275 | #define CONFIG_SYS_BANK0_START 0x00000000 |
| 276 | #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) |
| 277 | #define CONFIG_SYS_BANK0_ENABLE 1 |
| 278 | #define CONFIG_SYS_BANK1_START 0x3ff00000 |
| 279 | #define CONFIG_SYS_BANK1_END 0x3fffffff |
| 280 | #define CONFIG_SYS_BANK1_ENABLE 0 |
| 281 | #define CONFIG_SYS_BANK2_START 0x3ff00000 |
| 282 | #define CONFIG_SYS_BANK2_END 0x3fffffff |
| 283 | #define CONFIG_SYS_BANK2_ENABLE 0 |
| 284 | #define CONFIG_SYS_BANK3_START 0x3ff00000 |
| 285 | #define CONFIG_SYS_BANK3_END 0x3fffffff |
| 286 | #define CONFIG_SYS_BANK3_ENABLE 0 |
| 287 | #define CONFIG_SYS_BANK4_START 0x00000000 |
| 288 | #define CONFIG_SYS_BANK4_END 0x00000000 |
| 289 | #define CONFIG_SYS_BANK4_ENABLE 0 |
| 290 | #define CONFIG_SYS_BANK5_START 0x00000000 |
| 291 | #define CONFIG_SYS_BANK5_END 0x00000000 |
| 292 | #define CONFIG_SYS_BANK5_ENABLE 0 |
| 293 | #define CONFIG_SYS_BANK6_START 0x00000000 |
| 294 | #define CONFIG_SYS_BANK6_END 0x00000000 |
| 295 | #define CONFIG_SYS_BANK6_ENABLE 0 |
| 296 | #define CONFIG_SYS_BANK7_START 0x00000000 |
| 297 | #define CONFIG_SYS_BANK7_END 0x00000000 |
| 298 | #define CONFIG_SYS_BANK7_ENABLE 0 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 299 | /* |
| 300 | * Memory bank enable bitmask, specifying which of the banks defined above |
| 301 | are actually present. MSB is for bank #7, LSB is for bank #0. |
| 302 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 303 | #define CONFIG_SYS_BANK_ENABLE 0x01 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 304 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 305 | #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 306 | /* see 8240 book for bit definitions */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 307 | #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 308 | /* currently accessed page in memory */ |
| 309 | /* see 8240 book for details */ |
| 310 | |
| 311 | /* SDRAM 0 - 256MB */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 312 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 313 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 314 | |
| 315 | /* stack in DCACHE @ 1GB (no backing mem) */ |
| 316 | #if defined(USE_DINK32) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 317 | #define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 ) |
| 318 | #define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K ) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 319 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 320 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 321 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 322 | #endif |
| 323 | |
| 324 | /* PCI memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 325 | #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
| 326 | #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 327 | |
| 328 | /* Flash, config addrs, etc */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 329 | #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
| 330 | #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 331 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 332 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
| 333 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U |
| 334 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
| 335 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U |
| 336 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
| 337 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
| 338 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
| 339 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 340 | |
| 341 | /* |
| 342 | * For booting Linux, the board info and command line data |
| 343 | * have to be in the first 8 MB of memory, since this is |
| 344 | * the maximum mapped by the Linux kernel during initialization. |
| 345 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 346 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 347 | /*----------------------------------------------------------------------- |
| 348 | * FLASH organization |
| 349 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 350 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 351 | #define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 352 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 353 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 354 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 355 | |
| 356 | /*----------------------------------------------------------------------- |
| 357 | * Cache Configuration |
| 358 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 359 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ |
Jon Loeliger | d866df3 | 2007-07-08 15:02:44 -0500 | [diff] [blame] | 360 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 361 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 362 | #endif |
| 363 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 364 | /* values according to the manual */ |
| 365 | |
| 366 | #define CONFIG_DRAM_50MHZ 1 |
| 367 | #define CONFIG_SDRAM_50MHZ |
| 368 | |
| 369 | #undef NR_8259_INTS |
| 370 | #define NR_8259_INTS 1 |
| 371 | |
| 372 | |
| 373 | #define CONFIG_DISK_SPINUP_TIME 1000000 |
| 374 | |
| 375 | |
| 376 | #endif /* __CONFIG_H */ |