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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk8d5d28a2005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/* ------------------------------------------------------------------------- */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21
wdenkc6097192002-11-03 00:24:07 +000022#define CONFIG_MPC8245 1
23#define CONFIG_SANDPOINT 1
24
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFF00000
Wolfgang Denk79362d32010-11-23 23:48:56 +010026#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds"
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020027
wdenkc6097192002-11-03 00:24:07 +000028#if 0
29#define USE_DINK32 1
30#else
31#undef USE_DINK32
32#endif
33
34#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
35#define CONFIG_BAUDRATE 9600
36#define CONFIG_DRAM_SPEED 100 /* MHz */
37
wdenk8d5d28a2005-04-02 22:37:54 +000038#define CONFIG_TIMESTAMP /* Print image info with timestamp */
39
wdenkc6097192002-11-03 00:24:07 +000040
Jon Loeligerd866df32007-07-08 15:02:44 -050041/*
Jon Loeligerbeb9ff42007-07-10 09:22:23 -050042 * BOOTP options
43 */
44#define CONFIG_BOOTP_BOOTFILESIZE
45#define CONFIG_BOOTP_BOOTPATH
46#define CONFIG_BOOTP_GATEWAY
47#define CONFIG_BOOTP_HOSTNAME
48
49
50/*
Jon Loeligerd866df32007-07-08 15:02:44 -050051 * Command line configuration.
52 */
53#include <config_cmd_default.h>
54
55#define CONFIG_CMD_DHCP
56#define CONFIG_CMD_ELF
57#define CONFIG_CMD_I2C
58#define CONFIG_CMD_EEPROM
59#define CONFIG_CMD_NFS
60#define CONFIG_CMD_PCI
61#define CONFIG_CMD_SNTP
wdenkc6097192002-11-03 00:24:07 +000062
63
64/*
65 * Miscellaneous configurable options
66 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
69#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
70#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
71#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
72#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenkc6097192002-11-03 00:24:07 +000073
74/*-----------------------------------------------------------------------
75 * PCI stuff
76 *-----------------------------------------------------------------------
77 */
78#define CONFIG_PCI /* include pci support */
Gabor Juhosb4458732013-05-30 07:06:12 +000079#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc6097192002-11-03 00:24:07 +000080#undef CONFIG_PCI_PNP
81
wdenkc6097192002-11-03 00:24:07 +000082
83#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc6097192002-11-03 00:24:07 +000085#define CONFIG_NATSEMI
86#define CONFIG_NS8382X
87
88#define PCI_ENET0_IOADDR 0x80000000
89#define PCI_ENET0_MEMADDR 0x80000000
90#define PCI_ENET1_IOADDR 0x81000000
91#define PCI_ENET1_MEMADDR 0x81000000
92
93
94/*-----------------------------------------------------------------------
95 * Start addresses for the final memory configuration
96 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +000098 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_SDRAM_BASE 0x00000000
100#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenkc6097192002-11-03 00:24:07 +0000101
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +0000103
104#if defined (USE_DINK32)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105#define CONFIG_SYS_MONITOR_LEN 0x00030000
106#define CONFIG_SYS_MONITOR_BASE 0x00090000
107#define CONFIG_SYS_RAMBOOT 1
108#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200109#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
Wolfgang Denk0191e472010-10-26 14:34:52 +0200110#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000112#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#undef CONFIG_SYS_RAMBOOT
114#define CONFIG_SYS_MONITOR_LEN 0x00030000
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200115#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000116
wdenkc6097192002-11-03 00:24:07 +0000117
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200119#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk0191e472010-10-26 14:34:52 +0200120#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000121
122#endif
123
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_FLASH_BASE 0xFFF00000
wdenkc6097192002-11-03 00:24:07 +0000125#if 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
wdenkc6097192002-11-03 00:24:07 +0000127#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200128#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
wdenkc6097192002-11-03 00:24:07 +0000129#endif
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200130#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200131#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
132#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000133
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
137#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000138
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkc6097192002-11-03 00:24:07 +0000140
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141#define CONFIG_SYS_ISA_MEM 0xFD000000
142#define CONFIG_SYS_ISA_IO 0xFE000000
wdenkc6097192002-11-03 00:24:07 +0000143
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
145#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
wdenkc6097192002-11-03 00:24:07 +0000146#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
147#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
148
149/*
150 * select i2c support configuration
151 *
152 * Supported configurations are {none, software, hardware} drivers.
153 * If the software driver is chosen, there are some additional
154 * configuration items that the driver uses to drive the port pins.
155 */
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100156#define CONFIG_HARD_I2C 1 /* To enable I2C support */
157#undef CONFIG_SYS_I2C_SOFT
158#define CONFIG_SYS_I2C_SPEED 400000
159#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000160
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100161#ifdef CONFIG_SYS_I2C_SOFT
wdenkc6097192002-11-03 00:24:07 +0000162#error "Soft I2C is not configured properly. Please review!"
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100163#define CONFIG_SYS_I2C
164#define CONFIG_SYS_I2C_SOFT_SPEED 50000
165#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenkc6097192002-11-03 00:24:07 +0000166#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
167#define I2C_ACTIVE (iop->pdir |= 0x00010000)
168#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
169#define I2C_READ ((iop->pdat & 0x00010000) != 0)
170#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
171 else iop->pdat &= ~0x00010000
172#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
173 else iop->pdat &= ~0x00020000
174#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100175#endif /* CONFIG_SYS_I2C_SOFT */
wdenkc6097192002-11-03 00:24:07 +0000176
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
178#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
179#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
180#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000181
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
wdenkc6097192002-11-03 00:24:07 +0000183
184/*-----------------------------------------------------------------------
185 * Definitions for initial stack pointer and data area (in DPRAM)
186 */
187
188
Wolfgang Denk41364282010-11-23 23:17:18 +0100189/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
191#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
192#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
wdenkc6097192002-11-03 00:24:07 +0000193
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
195#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000196
197/*
198 * NS87308 Configuration
199 */
Jean-Christophe PLAGNIOL-VILLARDa44b9aa2008-08-13 01:40:40 +0200200#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
wdenkc6097192002-11-03 00:24:07 +0000201
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_NS87308_BADDR_10 1
wdenkc6097192002-11-03 00:24:07 +0000203
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
205 CONFIG_SYS_NS87308_UART2 | \
206 CONFIG_SYS_NS87308_POWRMAN | \
207 CONFIG_SYS_NS87308_RTC_APC )
wdenkc6097192002-11-03 00:24:07 +0000208
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#undef CONFIG_SYS_NS87308_PS2MOD
wdenkc6097192002-11-03 00:24:07 +0000210
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
212#define CONFIG_SYS_NS87308_CS0_CONF 0x30
213#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
214#define CONFIG_SYS_NS87308_CS1_CONF 0x30
215#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
216#define CONFIG_SYS_NS87308_CS2_CONF 0x30
wdenkc6097192002-11-03 00:24:07 +0000217
218/*
219 * NS16550 Configuration
220 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_NS16550
222#define CONFIG_SYS_NS16550_SERIAL
wdenkc6097192002-11-03 00:24:07 +0000223
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkc6097192002-11-03 00:24:07 +0000225
wdenk37bdfdf2004-06-10 21:55:33 +0000226#if (CONFIG_CONS_INDEX > 2)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
wdenk37bdfdf2004-06-10 21:55:33 +0000228#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200229#define CONFIG_SYS_NS16550_CLK 1843200
wdenk37bdfdf2004-06-10 21:55:33 +0000230#endif
wdenk9e930b62004-06-19 21:19:10 +0000231
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
233#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
234#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
235#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
wdenkc6097192002-11-03 00:24:07 +0000236
237/*
238 * Low Level Configuration Settings
239 * (address mappings, register initial values, etc.)
240 * You should know what you are doing if you make changes here.
241 */
242
243#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
244
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
246#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
wdenkc6097192002-11-03 00:24:07 +0000247
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200248#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
wdenkc6097192002-11-03 00:24:07 +0000249
250/* the following are for SDRAM only*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
252#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
253#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
254#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
255#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
256#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
257#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
258#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
wdenkc6097192002-11-03 00:24:07 +0000259#if 0
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200260#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
wdenkc6097192002-11-03 00:24:07 +0000261#endif
262
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200263#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
264#define CONFIG_SYS_EXTROM 1
265#define CONFIG_SYS_REGDIMM 0
wdenkc6097192002-11-03 00:24:07 +0000266
267
268/* memory bank settings*/
269/*
270 * only bits 20-29 are actually used from these vales to set the
271 * start/end address the upper two bits will be 0, and the lower 20
272 * bits will be set to 0x00000 for a start address, or 0xfffff for an
273 * end address
274 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200275#define CONFIG_SYS_BANK0_START 0x00000000
276#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
277#define CONFIG_SYS_BANK0_ENABLE 1
278#define CONFIG_SYS_BANK1_START 0x3ff00000
279#define CONFIG_SYS_BANK1_END 0x3fffffff
280#define CONFIG_SYS_BANK1_ENABLE 0
281#define CONFIG_SYS_BANK2_START 0x3ff00000
282#define CONFIG_SYS_BANK2_END 0x3fffffff
283#define CONFIG_SYS_BANK2_ENABLE 0
284#define CONFIG_SYS_BANK3_START 0x3ff00000
285#define CONFIG_SYS_BANK3_END 0x3fffffff
286#define CONFIG_SYS_BANK3_ENABLE 0
287#define CONFIG_SYS_BANK4_START 0x00000000
288#define CONFIG_SYS_BANK4_END 0x00000000
289#define CONFIG_SYS_BANK4_ENABLE 0
290#define CONFIG_SYS_BANK5_START 0x00000000
291#define CONFIG_SYS_BANK5_END 0x00000000
292#define CONFIG_SYS_BANK5_ENABLE 0
293#define CONFIG_SYS_BANK6_START 0x00000000
294#define CONFIG_SYS_BANK6_END 0x00000000
295#define CONFIG_SYS_BANK6_ENABLE 0
296#define CONFIG_SYS_BANK7_START 0x00000000
297#define CONFIG_SYS_BANK7_END 0x00000000
298#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000299/*
300 * Memory bank enable bitmask, specifying which of the banks defined above
301 are actually present. MSB is for bank #7, LSB is for bank #0.
302 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#define CONFIG_SYS_BANK_ENABLE 0x01
wdenkc6097192002-11-03 00:24:07 +0000304
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
wdenkc6097192002-11-03 00:24:07 +0000306 /* see 8240 book for bit definitions */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200307#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
wdenkc6097192002-11-03 00:24:07 +0000308 /* currently accessed page in memory */
309 /* see 8240 book for details */
310
311/* SDRAM 0 - 256MB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200312#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
313#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000314
315/* stack in DCACHE @ 1GB (no backing mem) */
316#if defined(USE_DINK32)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200317#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
318#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
wdenkc6097192002-11-03 00:24:07 +0000319#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200320#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
321#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000322#endif
323
324/* PCI memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200325#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
326#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000327
328/* Flash, config addrs, etc */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200329#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
330#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000331
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200332#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
333#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
334#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
335#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
336#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
337#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
338#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
339#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000340
341/*
342 * For booting Linux, the board info and command line data
343 * have to be in the first 8 MB of memory, since this is
344 * the maximum mapped by the Linux kernel during initialization.
345 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200346#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000347/*-----------------------------------------------------------------------
348 * FLASH organization
349 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200350#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
351#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000352
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200353#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
354#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000355
356/*-----------------------------------------------------------------------
357 * Cache Configuration
358 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200359#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
Jon Loeligerd866df32007-07-08 15:02:44 -0500360#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200361# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000362#endif
363
wdenkc6097192002-11-03 00:24:07 +0000364/* values according to the manual */
365
366#define CONFIG_DRAM_50MHZ 1
367#define CONFIG_SDRAM_50MHZ
368
369#undef NR_8259_INTS
370#define NR_8259_INTS 1
371
372
373#define CONFIG_DISK_SPINUP_TIME 1000000
374
375
376#endif /* __CONFIG_H */