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git01.mediatek.com / filogic / uboot / feaae760d3ba7f49701e4c58ba0cbc481a99f542 / . / board / freescale / ls2080ardb / eth_ls2080rdb.c
blob: 799799c251c2f21ed9eb8fe57ee00b4bc7df7bb4 [file] [log] [blame]
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530[diff] [blame]1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <command.h>
10#include <netdev.h>
11#include <malloc.h>
12#include <fsl_mdio.h>
13#include <miiphy.h>
14#include <phy.h>
15#include <fm_eth.h>
16#include <asm/io.h>
Prabhakar Kushwaha7b3a6bc2015-06-28 11:03:59 +0530[diff] [blame]17#include <exports.h>
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530[diff] [blame]18#include <asm/arch/fsl_serdes.h>
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530[diff] [blame]19#include <fsl-mc/ldpaa_wriop.h>
20
Prabhakar Kushwaha7b3a6bc2015-06-28 11:03:59 +0530[diff] [blame]21DECLARE_GLOBAL_DATA_PTR;
22
Pratiyush Mohan Srivastava9abba112016-01-20 12:29:03 +0530[diff] [blame]23#define MC_BOOT_ENV_VAR "mcinitcmd"
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530[diff] [blame]24int board_eth_init(bd_t *bis)
25{
26#if defined(CONFIG_FSL_MC_ENET)
Pratiyush Mohan Srivastava9abba112016-01-20 12:29:03 +0530[diff] [blame]27 char *mc_boot_env_var;
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530[diff] [blame]28 int i, interface;
29 struct memac_mdio_info mdio_info;
30 struct mii_dev *dev;
31 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
32 u32 srds_s1;
33 struct memac_mdio_controller *reg;
34
35 srds_s1 = in_le32(&gur->rcwsr[28]) &
36 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
37 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
38
39 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
40 mdio_info.regs = reg;
41 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
42
43 /* Register the EMI 1 */
44 fm_memac_mdio_init(bis, &mdio_info);
45
46 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
47 mdio_info.regs = reg;
48 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
49
50 /* Register the EMI 2 */
51 fm_memac_mdio_init(bis, &mdio_info);
52
53 switch (srds_s1) {
54 case 0x2A:
55 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
56 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
57 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
58 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
59 wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
60 wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
61 wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
62 wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
63
64 break;
65 default:
Prabhakar Kushwaha122bcfd2015-11-09 16:42:07 +0530[diff] [blame]66 printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530[diff] [blame]67 srds_s1);
68 break;
69 }
70
71 for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
72 interface = wriop_get_enet_if(i);
73 switch (interface) {
74 case PHY_INTERFACE_MODE_XGMII:
75 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
76 wriop_set_mdio(i, dev);
77 break;
78 default:
79 break;
80 }
81 }
82
83 for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
84 switch (wriop_get_enet_if(i)) {
85 case PHY_INTERFACE_MODE_XGMII:
86 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
87 wriop_set_mdio(i, dev);
88 break;
89 default:
90 break;
91 }
92 }
93
Pratiyush Mohan Srivastava9abba112016-01-20 12:29:03 +0530[diff] [blame]94 mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
95 if (mc_boot_env_var)
96 run_command_list(mc_boot_env_var, -1, 0);
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530[diff] [blame]97 cpu_eth_init(bis);
98#endif /* CONFIG_FMAN_ENET */
99
Prabhakar Kushwaha7b3a6bc2015-06-28 11:03:59 +0530[diff] [blame]100#ifdef CONFIG_PHY_AQUANTIA
101 /*
102 * Export functions to be used by AQ firmware
103 * upload application
104 */
105 gd->jt->strcpy = strcpy;
106 gd->jt->mdelay = mdelay;
107 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
108 gd->jt->phy_find_by_mask = phy_find_by_mask;
109 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
110 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
111#endif
Prabhakar Kushwahab0b41892015-05-28 14:53:54 +0530[diff] [blame]112 return pci_eth_init(bis);
113}