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git01.mediatek.com / filogic / uboot / fe960be5e630c41c0a7e14c6295ed1f2f30535c2 / . / arch / arm / dts / am33xx.dtsi
blob: b26e21bd7ffb5814ec456a637ebda0651e15dadc [file] [log] [blame]
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/am33xx.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
19
20 aliases {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 cpu@0 {
44 compatible = "arm,cortex-a8";
45 device_type = "cpu";
46 reg = <0>;
47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
66 };
67 };
68
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]74 /*
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]86 /*
87 * XXX: Use a flat representation of the AM33XX interconnect.
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]88 * The real AM33XX interconnect network is quite complex. Since
89 * it will not bring real advantage to represent that in DT
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]90 * for the moment, just use a fake OCP bus entry to represent
91 * the whole bus hierarchy.
92 */
93 ocp {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 ranges;
98 ti,hwmods = "l3_main";
99
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]100 l4_wkup: l4_wkup@44c00000 {
101 compatible = "ti,am3-l4-wkup", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 0x44c00000 0x280000>;
105
106 prcm: prcm@200000 {
107 compatible = "ti,am3-prcm";
108 reg = <0x200000 0x4000>;
109
110 prcm_clocks: clocks {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 };
114
115 prcm_clockdomains: clockdomains {
116 };
117 };
118
119 scm: scm@210000 {
120 compatible = "ti,am3-scm", "simple-bus";
121 reg = <0x210000 0x2000>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges = <0 0x210000 0x2000>;
125
126 am33xx_pinmux: pinmux@800 {
127 compatible = "pinctrl-single";
128 reg = <0x800 0x238>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = <0x7f>;
133 };
134
135 scm_conf: scm_conf@0 {
136 compatible = "syscon";
137 reg = <0x0 0x800>;
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 scm_clocks: clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 };
145 };
146
147 scm_clockdomains: clockdomains {
148 };
149 };
150 };
151
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]152 intc: interrupt-controller@48200000 {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]153 compatible = "ti,am33xx-intc";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]154 interrupt-controller;
155 #interrupt-cells = <1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]156 reg = <0x48200000 0x1000>;
157 };
158
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]159 edma: edma@49000000 {
160 compatible = "ti,edma3";
161 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
162 reg = <0x49000000 0x10000>,
163 <0x44e10f90 0x40>;
164 interrupts = <12 13 14>;
165 #dma-cells = <1>;
166 };
167
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]168 gpio0: gpio@44e07000 {
169 compatible = "ti,omap4-gpio";
170 ti,hwmods = "gpio1";
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]174 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]175 reg = <0x44e07000 0x1000>;
176 interrupts = <96>;
177 };
178
179 gpio1: gpio@4804c000 {
180 compatible = "ti,omap4-gpio";
181 ti,hwmods = "gpio2";
182 gpio-controller;
183 #gpio-cells = <2>;
184 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]185 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]186 reg = <0x4804c000 0x1000>;
187 interrupts = <98>;
188 };
189
190 gpio2: gpio@481ac000 {
191 compatible = "ti,omap4-gpio";
192 ti,hwmods = "gpio3";
193 gpio-controller;
194 #gpio-cells = <2>;
195 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]196 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]197 reg = <0x481ac000 0x1000>;
198 interrupts = <32>;
199 };
200
201 gpio3: gpio@481ae000 {
202 compatible = "ti,omap4-gpio";
203 ti,hwmods = "gpio4";
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]207 #interrupt-cells = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]208 reg = <0x481ae000 0x1000>;
209 interrupts = <62>;
210 };
211
212 uart0: serial@44e09000 {
213 compatible = "ti,omap3-uart";
214 ti,hwmods = "uart1";
215 clock-frequency = <48000000>;
216 reg = <0x44e09000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]217 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]218 interrupts = <72>;
219 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]220 dmas = <&edma 26>, <&edma 27>;
221 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]222 };
223
224 uart1: serial@48022000 {
225 compatible = "ti,omap3-uart";
226 ti,hwmods = "uart2";
227 clock-frequency = <48000000>;
228 reg = <0x48022000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]229 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]230 interrupts = <73>;
231 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]232 dmas = <&edma 28>, <&edma 29>;
233 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]234 };
235
236 uart2: serial@48024000 {
237 compatible = "ti,omap3-uart";
238 ti,hwmods = "uart3";
239 clock-frequency = <48000000>;
240 reg = <0x48024000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]241 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]242 interrupts = <74>;
243 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]244 dmas = <&edma 30>, <&edma 31>;
245 dma-names = "tx", "rx";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]246 };
247
248 uart3: serial@481a6000 {
249 compatible = "ti,omap3-uart";
250 ti,hwmods = "uart4";
251 clock-frequency = <48000000>;
252 reg = <0x481a6000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]253 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]254 interrupts = <44>;
255 status = "disabled";
256 };
257
258 uart4: serial@481a8000 {
259 compatible = "ti,omap3-uart";
260 ti,hwmods = "uart5";
261 clock-frequency = <48000000>;
262 reg = <0x481a8000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]263 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]264 interrupts = <45>;
265 status = "disabled";
266 };
267
268 uart5: serial@481aa000 {
269 compatible = "ti,omap3-uart";
270 ti,hwmods = "uart6";
271 clock-frequency = <48000000>;
272 reg = <0x481aa000 0x2000>;
Mugunthan V N65634e82015-11-26 14:49:10 +0530[diff] [blame]273 reg-shift = <2>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]274 interrupts = <46>;
275 status = "disabled";
276 };
277
278 i2c0: i2c@44e0b000 {
279 compatible = "ti,omap4-i2c";
280 #address-cells = <1>;
281 #size-cells = <0>;
282 ti,hwmods = "i2c1";
283 reg = <0x44e0b000 0x1000>;
284 interrupts = <70>;
285 status = "disabled";
286 };
287
288 i2c1: i2c@4802a000 {
289 compatible = "ti,omap4-i2c";
290 #address-cells = <1>;
291 #size-cells = <0>;
292 ti,hwmods = "i2c2";
293 reg = <0x4802a000 0x1000>;
294 interrupts = <71>;
295 status = "disabled";
296 };
297
298 i2c2: i2c@4819c000 {
299 compatible = "ti,omap4-i2c";
300 #address-cells = <1>;
301 #size-cells = <0>;
302 ti,hwmods = "i2c3";
303 reg = <0x4819c000 0x1000>;
304 interrupts = <30>;
305 status = "disabled";
306 };
307
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]308 mmc1: mmc@48060000 {
309 compatible = "ti,omap4-hsmmc";
310 ti,hwmods = "mmc1";
311 ti,dual-volt;
312 ti,needs-special-reset;
313 ti,needs-special-hs-handling;
314 dmas = <&edma 24
315 &edma 25>;
316 dma-names = "tx", "rx";
317 interrupts = <64>;
318 interrupt-parent = <&intc>;
319 reg = <0x48060000 0x1000>;
320 status = "disabled";
321 };
322
323 mmc2: mmc@481d8000 {
324 compatible = "ti,omap4-hsmmc";
325 ti,hwmods = "mmc2";
326 ti,needs-special-reset;
327 dmas = <&edma 2
328 &edma 3>;
329 dma-names = "tx", "rx";
330 interrupts = <28>;
331 interrupt-parent = <&intc>;
332 reg = <0x481d8000 0x1000>;
333 status = "disabled";
334 };
335
336 mmc3: mmc@47810000 {
337 compatible = "ti,omap4-hsmmc";
338 ti,hwmods = "mmc3";
339 ti,needs-special-reset;
340 interrupts = <29>;
341 interrupt-parent = <&intc>;
342 reg = <0x47810000 0x1000>;
343 status = "disabled";
344 };
345
346 hwspinlock: spinlock@480ca000 {
347 compatible = "ti,omap4-hwspinlock";
348 reg = <0x480ca000 0x1000>;
349 ti,hwmods = "spinlock";
350 #hwlock-cells = <1>;
351 };
352
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]353 wdt2: wdt@44e35000 {
354 compatible = "ti,omap3-wdt";
355 ti,hwmods = "wd_timer2";
356 reg = <0x44e35000 0x1000>;
357 interrupts = <91>;
358 };
359
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]360 dcan0: can@481cc000 {
361 compatible = "ti,am3352-d_can";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]362 ti,hwmods = "d_can0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]363 reg = <0x481cc000 0x2000>;
364 clocks = <&dcan0_fck>;
365 clock-names = "fck";
366 syscon-raminit = <&scm_conf 0x644 0>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]367 interrupts = <52>;
368 status = "disabled";
369 };
370
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]371 dcan1: can@481d0000 {
372 compatible = "ti,am3352-d_can";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]373 ti,hwmods = "d_can1";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]374 reg = <0x481d0000 0x2000>;
375 clocks = <&dcan1_fck>;
376 clock-names = "fck";
377 syscon-raminit = <&scm_conf 0x644 1>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]378 interrupts = <55>;
379 status = "disabled";
380 };
381
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]382 mailbox: mailbox@480C8000 {
383 compatible = "ti,omap4-mailbox";
384 reg = <0x480C8000 0x200>;
385 interrupts = <77>;
386 ti,hwmods = "mailbox";
387 #mbox-cells = <1>;
388 ti,mbox-num-users = <4>;
389 ti,mbox-num-fifos = <8>;
390 mbox_wkupm3: wkup_m3 {
391 ti,mbox-tx = <0 0 0>;
392 ti,mbox-rx = <0 0 3>;
393 };
394 };
395
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]396 timer1: timer@44e31000 {
397 compatible = "ti,am335x-timer-1ms";
398 reg = <0x44e31000 0x400>;
399 interrupts = <67>;
400 ti,hwmods = "timer1";
401 ti,timer-alwon;
402 };
403
404 timer2: timer@48040000 {
405 compatible = "ti,am335x-timer";
406 reg = <0x48040000 0x400>;
407 interrupts = <68>;
408 ti,hwmods = "timer2";
409 };
410
411 timer3: timer@48042000 {
412 compatible = "ti,am335x-timer";
413 reg = <0x48042000 0x400>;
414 interrupts = <69>;
415 ti,hwmods = "timer3";
416 };
417
418 timer4: timer@48044000 {
419 compatible = "ti,am335x-timer";
420 reg = <0x48044000 0x400>;
421 interrupts = <92>;
422 ti,hwmods = "timer4";
423 ti,timer-pwm;
424 };
425
426 timer5: timer@48046000 {
427 compatible = "ti,am335x-timer";
428 reg = <0x48046000 0x400>;
429 interrupts = <93>;
430 ti,hwmods = "timer5";
431 ti,timer-pwm;
432 };
433
434 timer6: timer@48048000 {
435 compatible = "ti,am335x-timer";
436 reg = <0x48048000 0x400>;
437 interrupts = <94>;
438 ti,hwmods = "timer6";
439 ti,timer-pwm;
440 };
441
442 timer7: timer@4804a000 {
443 compatible = "ti,am335x-timer";
444 reg = <0x4804a000 0x400>;
445 interrupts = <95>;
446 ti,hwmods = "timer7";
447 ti,timer-pwm;
448 };
449
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]450 rtc: rtc@44e3e000 {
451 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]452 reg = <0x44e3e000 0x1000>;
453 interrupts = <75
454 76>;
455 ti,hwmods = "rtc";
456 };
457
458 spi0: spi@48030000 {
459 compatible = "ti,omap4-mcspi";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 reg = <0x48030000 0x400>;
463 interrupts = <65>;
464 ti,spi-num-cs = <2>;
465 ti,hwmods = "spi0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]466 dmas = <&edma 16
467 &edma 17
468 &edma 18
469 &edma 19>;
470 dma-names = "tx0", "rx0", "tx1", "rx1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]471 status = "disabled";
472 };
473
474 spi1: spi@481a0000 {
475 compatible = "ti,omap4-mcspi";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 reg = <0x481a0000 0x400>;
479 interrupts = <125>;
480 ti,spi-num-cs = <2>;
481 ti,hwmods = "spi1";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]482 dmas = <&edma 42
483 &edma 43
484 &edma 44
485 &edma 45>;
486 dma-names = "tx0", "rx0", "tx1", "rx1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]487 status = "disabled";
488 };
489
490 usb: usb@47400000 {
491 compatible = "ti,am33xx-usb";
492 reg = <0x47400000 0x1000>;
493 ranges;
494 #address-cells = <1>;
495 #size-cells = <1>;
496 ti,hwmods = "usb_otg_hs";
497 status = "disabled";
498
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]499 usb_ctrl_mod: control@44e10620 {
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]500 compatible = "ti,am335x-usb-ctrl-module";
501 reg = <0x44e10620 0x10
502 0x44e10648 0x4>;
503 reg-names = "phy_ctrl", "wakeup";
504 status = "disabled";
505 };
506
507 usb0_phy: usb-phy@47401300 {
508 compatible = "ti,am335x-usb-phy";
509 reg = <0x47401300 0x100>;
510 reg-names = "phy";
511 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]512 ti,ctrl_mod = <&usb_ctrl_mod>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]513 };
514
515 usb0: usb@47401000 {
516 compatible = "ti,musb-am33xx";
517 status = "disabled";
518 reg = <0x47401400 0x400
519 0x47401000 0x200>;
520 reg-names = "mc", "control";
521
522 interrupts = <18>;
523 interrupt-names = "mc";
524 dr_mode = "otg";
525 mentor,multipoint = <1>;
526 mentor,num-eps = <16>;
527 mentor,ram-bits = <12>;
528 mentor,power = <500>;
529 phys = <&usb0_phy>;
530
531 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
532 &cppi41dma 2 0 &cppi41dma 3 0
533 &cppi41dma 4 0 &cppi41dma 5 0
534 &cppi41dma 6 0 &cppi41dma 7 0
535 &cppi41dma 8 0 &cppi41dma 9 0
536 &cppi41dma 10 0 &cppi41dma 11 0
537 &cppi41dma 12 0 &cppi41dma 13 0
538 &cppi41dma 14 0 &cppi41dma 0 1
539 &cppi41dma 1 1 &cppi41dma 2 1
540 &cppi41dma 3 1 &cppi41dma 4 1
541 &cppi41dma 5 1 &cppi41dma 6 1
542 &cppi41dma 7 1 &cppi41dma 8 1
543 &cppi41dma 9 1 &cppi41dma 10 1
544 &cppi41dma 11 1 &cppi41dma 12 1
545 &cppi41dma 13 1 &cppi41dma 14 1>;
546 dma-names =
547 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
548 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
549 "rx14", "rx15",
550 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
551 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
552 "tx14", "tx15";
553 };
554
555 usb1_phy: usb-phy@47401b00 {
556 compatible = "ti,am335x-usb-phy";
557 reg = <0x47401b00 0x100>;
558 reg-names = "phy";
559 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]560 ti,ctrl_mod = <&usb_ctrl_mod>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]561 };
562
563 usb1: usb@47401800 {
564 compatible = "ti,musb-am33xx";
565 status = "disabled";
566 reg = <0x47401c00 0x400
567 0x47401800 0x200>;
568 reg-names = "mc", "control";
569 interrupts = <19>;
570 interrupt-names = "mc";
571 dr_mode = "otg";
572 mentor,multipoint = <1>;
573 mentor,num-eps = <16>;
574 mentor,ram-bits = <12>;
575 mentor,power = <500>;
576 phys = <&usb1_phy>;
577
578 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
579 &cppi41dma 17 0 &cppi41dma 18 0
580 &cppi41dma 19 0 &cppi41dma 20 0
581 &cppi41dma 21 0 &cppi41dma 22 0
582 &cppi41dma 23 0 &cppi41dma 24 0
583 &cppi41dma 25 0 &cppi41dma 26 0
584 &cppi41dma 27 0 &cppi41dma 28 0
585 &cppi41dma 29 0 &cppi41dma 15 1
586 &cppi41dma 16 1 &cppi41dma 17 1
587 &cppi41dma 18 1 &cppi41dma 19 1
588 &cppi41dma 20 1 &cppi41dma 21 1
589 &cppi41dma 22 1 &cppi41dma 23 1
590 &cppi41dma 24 1 &cppi41dma 25 1
591 &cppi41dma 26 1 &cppi41dma 27 1
592 &cppi41dma 28 1 &cppi41dma 29 1>;
593 dma-names =
594 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
595 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
596 "rx14", "rx15",
597 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
598 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
599 "tx14", "tx15";
600 };
601
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]602 cppi41dma: dma-controller@47402000 {
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]603 compatible = "ti,am3359-cppi41";
604 reg = <0x47400000 0x1000
605 0x47402000 0x1000
606 0x47403000 0x1000
607 0x47404000 0x4000>;
608 reg-names = "glue", "controller", "scheduler", "queuemgr";
609 interrupts = <17>;
610 interrupt-names = "glue";
611 #dma-cells = <2>;
612 #dma-channels = <30>;
613 #dma-requests = <256>;
614 status = "disabled";
615 };
616 };
617
618 epwmss0: epwmss@48300000 {
619 compatible = "ti,am33xx-pwmss";
620 reg = <0x48300000 0x10>;
621 ti,hwmods = "epwmss0";
622 #address-cells = <1>;
623 #size-cells = <1>;
624 status = "disabled";
625 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
626 0x48300180 0x48300180 0x80 /* EQEP */
627 0x48300200 0x48300200 0x80>; /* EHRPWM */
628
629 ecap0: ecap@48300100 {
630 compatible = "ti,am33xx-ecap";
631 #pwm-cells = <3>;
632 reg = <0x48300100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]633 interrupts = <31>;
634 interrupt-names = "ecap0";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]635 ti,hwmods = "ecap0";
636 status = "disabled";
637 };
638
639 ehrpwm0: ehrpwm@48300200 {
640 compatible = "ti,am33xx-ehrpwm";
641 #pwm-cells = <3>;
642 reg = <0x48300200 0x80>;
643 ti,hwmods = "ehrpwm0";
644 status = "disabled";
645 };
646 };
647
648 epwmss1: epwmss@48302000 {
649 compatible = "ti,am33xx-pwmss";
650 reg = <0x48302000 0x10>;
651 ti,hwmods = "epwmss1";
652 #address-cells = <1>;
653 #size-cells = <1>;
654 status = "disabled";
655 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
656 0x48302180 0x48302180 0x80 /* EQEP */
657 0x48302200 0x48302200 0x80>; /* EHRPWM */
658
659 ecap1: ecap@48302100 {
660 compatible = "ti,am33xx-ecap";
661 #pwm-cells = <3>;
662 reg = <0x48302100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]663 interrupts = <47>;
664 interrupt-names = "ecap1";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]665 ti,hwmods = "ecap1";
666 status = "disabled";
667 };
668
669 ehrpwm1: ehrpwm@48302200 {
670 compatible = "ti,am33xx-ehrpwm";
671 #pwm-cells = <3>;
672 reg = <0x48302200 0x80>;
673 ti,hwmods = "ehrpwm1";
674 status = "disabled";
675 };
676 };
677
678 epwmss2: epwmss@48304000 {
679 compatible = "ti,am33xx-pwmss";
680 reg = <0x48304000 0x10>;
681 ti,hwmods = "epwmss2";
682 #address-cells = <1>;
683 #size-cells = <1>;
684 status = "disabled";
685 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
686 0x48304180 0x48304180 0x80 /* EQEP */
687 0x48304200 0x48304200 0x80>; /* EHRPWM */
688
689 ecap2: ecap@48304100 {
690 compatible = "ti,am33xx-ecap";
691 #pwm-cells = <3>;
692 reg = <0x48304100 0x80>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]693 interrupts = <61>;
694 interrupt-names = "ecap2";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]695 ti,hwmods = "ecap2";
696 status = "disabled";
697 };
698
699 ehrpwm2: ehrpwm@48304200 {
700 compatible = "ti,am33xx-ehrpwm";
701 #pwm-cells = <3>;
702 reg = <0x48304200 0x80>;
703 ti,hwmods = "ehrpwm2";
704 status = "disabled";
705 };
706 };
707
708 mac: ethernet@4a100000 {
709 compatible = "ti,cpsw";
710 ti,hwmods = "cpgmac0";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]711 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
712 clock-names = "fck", "cpts";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]713 cpdma_channels = <8>;
714 ale_entries = <1024>;
715 bd_ram_size = <0x2000>;
716 no_bd_ram = <0>;
717 rx_descs = <64>;
718 mac_control = <0x20>;
719 slaves = <2>;
720 active_slave = <0>;
721 cpts_clock_mult = <0x80000000>;
722 cpts_clock_shift = <29>;
723 reg = <0x4a100000 0x800
724 0x4a101200 0x100>;
725 #address-cells = <1>;
726 #size-cells = <1>;
727 interrupt-parent = <&intc>;
728 /*
729 * c0_rx_thresh_pend
730 * c0_rx_pend
731 * c0_tx_pend
732 * c0_misc_pend
733 */
734 interrupts = <40 41 42 43>;
735 ranges;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]736 syscon = <&scm_conf>;
737 status = "disabled";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]738
739 davinci_mdio: mdio@4a101000 {
740 compatible = "ti,davinci_mdio";
741 #address-cells = <1>;
742 #size-cells = <0>;
743 ti,hwmods = "davinci_mdio";
744 bus_freq = <1000000>;
745 reg = <0x4a101000 0x100>;
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]746 status = "disabled";
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]747 };
748
749 cpsw_emac0: slave@4a100200 {
750 /* Filled in by U-Boot */
751 mac-address = [ 00 00 00 00 00 00 ];
752 };
753
754 cpsw_emac1: slave@4a100300 {
755 /* Filled in by U-Boot */
756 mac-address = [ 00 00 00 00 00 00 ];
757 };
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]758
759 phy_sel: cpsw-phy-sel@44e10650 {
760 compatible = "ti,am3352-cpsw-phy-sel";
761 reg= <0x44e10650 0x4>;
762 reg-names = "gmii-sel";
763 };
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]764 };
765
766 ocmcram: ocmcram@40300000 {
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]767 compatible = "mmio-sram";
768 reg = <0x40300000 0x10000>; /* 64k */
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]769 };
770
771 wkup_m3: wkup_m3@44d00000 {
772 compatible = "ti,am3353-wkup-m3";
773 reg = <0x44d00000 0x4000 /* M3 UMEM */
774 0x44d80000 0x2000>; /* M3 DMEM */
775 ti,hwmods = "wkup_m3";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]776 ti,no-reset-on-init;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]777 };
778
779 elm: elm@48080000 {
780 compatible = "ti,am3352-elm";
781 reg = <0x48080000 0x2000>;
782 interrupts = <4>;
783 ti,hwmods = "elm";
784 status = "disabled";
785 };
786
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]787 lcdc: lcdc@4830e000 {
788 compatible = "ti,am33xx-tilcdc";
789 reg = <0x4830e000 0x1000>;
790 interrupt-parent = <&intc>;
791 interrupts = <36>;
792 ti,hwmods = "lcdc";
793 status = "disabled";
794 };
795
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]796 tscadc: tscadc@44e0d000 {
797 compatible = "ti,am3359-tscadc";
798 reg = <0x44e0d000 0x1000>;
799 interrupt-parent = <&intc>;
800 interrupts = <16>;
801 ti,hwmods = "adc_tsc";
802 status = "disabled";
803
804 tsc {
805 compatible = "ti,am3359-tsc";
806 };
807 am335x_adc: adc {
808 #io-channel-cells = <1>;
809 compatible = "ti,am3359-adc";
810 };
811 };
812
813 gpmc: gpmc@50000000 {
814 compatible = "ti,am3352-gpmc";
815 ti,hwmods = "gpmc";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]816 ti,no-idle-on-init;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]817 reg = <0x50000000 0x2000>;
818 interrupts = <100>;
819 gpmc,num-cs = <7>;
820 gpmc,num-waitpins = <2>;
821 #address-cells = <2>;
822 #size-cells = <1>;
823 status = "disabled";
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]824 };
825
826 sham: sham@53100000 {
827 compatible = "ti,omap4-sham";
828 ti,hwmods = "sham";
829 reg = <0x53100000 0x200>;
830 interrupts = <109>;
831 dmas = <&edma 36>;
832 dma-names = "rx";
833 };
834
835 aes: aes@53500000 {
836 compatible = "ti,omap4-aes";
837 ti,hwmods = "aes";
838 reg = <0x53500000 0xa0>;
839 interrupts = <103>;
840 dmas = <&edma 6>,
841 <&edma 5>;
842 dma-names = "tx", "rx";
843 };
844
845 mcasp0: mcasp@48038000 {
846 compatible = "ti,am33xx-mcasp-audio";
847 ti,hwmods = "mcasp0";
848 reg = <0x48038000 0x2000>,
849 <0x46000000 0x400000>;
850 reg-names = "mpu", "dat";
851 interrupts = <80>, <81>;
852 interrupt-names = "tx", "rx";
853 status = "disabled";
854 dmas = <&edma 8>,
855 <&edma 9>;
856 dma-names = "tx", "rx";
857 };
858
859 mcasp1: mcasp@4803C000 {
860 compatible = "ti,am33xx-mcasp-audio";
861 ti,hwmods = "mcasp1";
862 reg = <0x4803C000 0x2000>,
863 <0x46400000 0x400000>;
864 reg-names = "mpu", "dat";
865 interrupts = <82>, <83>;
866 interrupt-names = "tx", "rx";
867 status = "disabled";
868 dmas = <&edma 10>,
869 <&edma 11>;
870 dma-names = "tx", "rx";
871 };
872
873 rng: rng@48310000 {
874 compatible = "ti,omap4-rng";
875 ti,hwmods = "rng";
876 reg = <0x48310000 0x2000>;
877 interrupts = <111>;
Simon Glassb37e8152014-06-02 22:04:55 -0600[diff] [blame]878 };
879 };
880};
Tom Rini5ba15962015-07-31 19:55:08 -0400[diff] [blame]881
882/include/ "am33xx-clocks.dtsi"