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Timur Tabi9b45b5a2010-06-14 15:28:24 -05001/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 * Author: Timur Tabi <timur@freescale.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or (at your option)
8 * any later version.
9 */
10
11#include <config.h>
12#include <common.h>
13#include <asm/io.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_serdes.h>
16
17#define SRDS1_MAX_LANES 4
18#define SRDS2_MAX_LANES 2
19
20static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
21 [0x00] = {NONE, NONE, NONE, NONE},
22 [0x01] = {NONE, NONE, NONE, NONE},
23 [0x02] = {NONE, NONE, NONE, NONE},
24 [0x03] = {NONE, NONE, NONE, NONE},
25 [0x04] = {NONE, NONE, NONE, NONE},
26 [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
27 [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
28 [0x09] = {PCIE1, NONE, NONE, NONE},
29 [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
30 [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
31 [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
32 [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
33 [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
34 [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
35 [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
36 [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
37 [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
38 [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
39 [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
40 [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
41 [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
42 [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
43 [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
44 [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
45};
46
47static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
48 [0x00] = {PCIE3, PCIE3},
49 [0x01] = {PCIE2, PCIE3},
50 [0x02] = {SATA1, SATA2},
51 [0x03] = {SGMII_TSEC1, SGMII_TSEC2},
52 [0x04] = {NONE, NONE},
53 [0x06] = {SATA1, SATA2},
54 [0x07] = {NONE, NONE},
55 [0x09] = {PCIE3, PCIE2},
56 [0x0a] = {SATA1, SATA2},
57 [0x0b] = {NONE, NONE},
58 [0x0d] = {PCIE3, PCIE2},
59 [0x0e] = {SATA1, SATA2},
60 [0x0f] = {NONE, NONE},
61 [0x15] = {SGMII_TSEC1, SGMII_TSEC2},
62 [0x16] = {SATA1, SATA2},
63 [0x17] = {NONE, NONE},
64 [0x18] = {PCIE3, PCIE3},
65 [0x19] = {SGMII_TSEC1, SGMII_TSEC2},
66 [0x1a] = {SATA1, SATA2},
67 [0x1b] = {NONE, NONE},
68 [0x1c] = {PCIE3, PCIE3},
69 [0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
70 [0x1e] = {SATA1, SATA2},
71 [0x1f] = {NONE, NONE},
72};
73
Timur Tabi9b45b5a2010-06-14 15:28:24 -050074int is_serdes_configured(enum srds_prtcl device)
75{
76 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
77 u32 pordevsr = in_be32(&gur->pordevsr);
78 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
79 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
80 unsigned int i;
81
82 debug("%s: dev = %d\n", __FUNCTION__, device);
83 debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg);
84
85 if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
86 printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg);
87 return 0;
88 }
89
90 for (i = 0; i < SRDS1_MAX_LANES; i++) {
91 if (serdes1_cfg_tbl[srds_cfg][i] == device)
92 return 1;
93 if (serdes2_cfg_tbl[srds_cfg][i] == device)
94 return 1;
95 }
96
97 return 0;
98}