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git01.mediatek.com / filogic / uboot / fe6296fcfca034e3a1704e520dd319c20dcf7b75 / . / board / Seagate / goflexhome / goflexhome.c
blob: 17c19053fa7eaca3b1a2fefb7eb93e7157786208 [file] [log] [blame]
Suriyan Ramasamif0ec8af2013-04-11 07:17:25 +0000[diff] [blame]1/*
2 * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
3 *
4 * Based on dockstar.c originally written by
5 * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
6 *
7 * Based on sheevaplug.c originally written by
8 * Prafulla Wadaskar <prafulla@marvell.com>
9 * (C) Copyright 2009
10 * Marvell Semiconductor <www.marvell.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 * MA 02110-1301 USA
29 */
30
31#include <common.h>
32#include <miiphy.h>
33#include <asm/arch/kirkwood.h>
34#include <asm/arch/mpp.h>
35#include <asm/arch/cpu.h>
36#include <asm/io.h>
37
38DECLARE_GLOBAL_DATA_PTR;
39
40int board_early_init_f(void)
41{
42 /* Multi-Purpose Pins Functionality configuration */
43 static const u32 kwmpp_config[] = {
44 MPP0_NF_IO2,
45 MPP1_NF_IO3,
46 MPP2_NF_IO4,
47 MPP3_NF_IO5,
48 MPP4_NF_IO6,
49 MPP5_NF_IO7,
50 MPP6_SYSRST_OUTn,
51 MPP7_GPO,
52 MPP8_UART0_RTS,
53 MPP9_UART0_CTS,
54 MPP10_UART0_TXD,
55 MPP11_UART0_RXD,
56 MPP12_SD_CLK,
57 MPP13_SD_CMD,
58 MPP14_SD_D0,
59 MPP15_SD_D1,
60 MPP16_SD_D2,
61 MPP17_SD_D3,
62 MPP18_NF_IO0,
63 MPP19_NF_IO1,
64 MPP20_GPIO,
65 MPP21_GPIO,
66 MPP22_GPIO,
67 MPP23_GPIO,
68 MPP24_GPIO,
69 MPP25_GPIO,
70 MPP26_GPIO,
71 MPP27_GPIO,
72 MPP28_GPIO,
73 MPP29_TSMP9,
74 MPP30_GPIO,
75 MPP31_GPIO,
76 MPP32_GPIO,
77 MPP33_GPIO,
78 MPP34_GPIO,
79 MPP35_GPIO,
80 MPP36_GPIO,
81 MPP37_GPIO,
82 MPP38_GPIO,
83 MPP39_GPIO,
84 MPP40_GPIO,
85 MPP41_GPIO,
86 MPP42_GPIO,
87 MPP43_GPIO,
88 MPP44_GPIO,
89 MPP45_GPIO,
90 MPP46_GPIO,
91 MPP47_GPIO,
92 MPP48_GPIO,
93 MPP49_GPIO,
94 0
95 };
96
97 /*
98 * default gpio configuration
99 * There are maximum 64 gpios controlled through 2 sets of registers
100 * the below configuration configures mainly initial LED status
101 */
102 kw_config_gpio(GOFLEXHOME_OE_VAL_LOW,
103 GOFLEXHOME_OE_VAL_HIGH,
104 GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
105 kirkwood_mpp_conf(kwmpp_config, NULL);
106 return 0;
107}
108
109int board_init(void)
110{
111 /*
112 * arch number of board
113 */
114 gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
115
116 /* address of boot parameters */
117 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
118
119 return 0;
120}
121
122#ifdef CONFIG_RESET_PHY_R
123/* Configure and enable MV88E1116 PHY */
124void reset_phy(void)
125{
126 u16 reg;
127 u16 devadr;
128 char *name = "egiga0";
129
130 if (miiphy_set_current_dev(name))
131 return;
132
133 /* command to read PHY dev address */
134 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
135 printf("Err..%s could not read PHY dev address\n",
136 __func__);
137 return;
138 }
139
140 /*
141 * Enable RGMII delay on Tx and Rx for CPU port
142 * Ref: sec 4.7.2 of chip datasheet
143 */
144 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
145 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
146 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
147 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
148 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
149
150 /* reset the phy */
151 miiphy_reset(name, devadr);
152
153 printf("88E1116 Initialized on %s\n", name);
154}
155#endif /* CONFIG_RESET_PHY_R */
156
157#define GREEN_LED (1 << 14)
158#define ORANGE_LED (1 << 15)
159#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
160#define NEITHER_LED 0
161
162static void set_leds(u32 leds, u32 blinking)
163{
164 struct kwgpio_registers *r;
165 u32 oe;
166 u32 bl;
167
168 r = (struct kwgpio_registers *)KW_GPIO1_BASE;
169 oe = readl(&r->oe) | BOTH_LEDS;
170 writel(oe & ~leds, &r->oe); /* active low */
171 bl = readl(&r->blink_en) & ~BOTH_LEDS;
172 writel(bl | blinking, &r->blink_en);
173}
174
175void show_boot_progress(int val)
176{
177 switch (val) {
178 case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
179 set_leds(BOTH_LEDS, NEITHER_LED);
180 break;
181 case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
182 set_leds(GREEN_LED, GREEN_LED);
183 break;
184 default:
185 if (val < 0) /* error */
186 set_leds(ORANGE_LED, ORANGE_LED);
187 break;
188 }
189}