Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / fe58675e04530215c35d7a39b357dbe2b9a23024 / . / configs / ls2080aqds_sdcard_defconfig
blob: df46a2208e054defc8b9952b68cc7d76246f869e [file] [log] [blame]
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]1CONFIG_ARM=y
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]2CONFIG_GIC_V3_ITS=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]3CONFIG_TARGET_LS2080AQDS=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x80400000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]5CONFIG_SYS_MALLOC_LEN=0x0220000
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]6CONFIG_SPL_LIBCOMMON_SUPPORT=y
7CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]8CONFIG_NR_DRAM_BANKS=3
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]9CONFIG_ENV_SIZE=0x20000
10CONFIG_ENV_OFFSET=0x300000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]11CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]12CONFIG_SPL_TEXT_BASE=0x1800a000
Tom Rini2c082ab2021-07-26 21:10:37 -0400[diff] [blame]13CONFIG_FSL_USE_PCA9547_MUX=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]14CONFIG_FSL_LS_PPA=y
Simon Glassb58bfe02021-08-08 12:20:09 -0600[diff] [blame]15CONFIG_SPL_MMC=y
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]16CONFIG_SPL_SERIAL=y
Simon Glass284cb9c2021-07-10 21:14:31 -0600[diff] [blame]17CONFIG_SPL_DRIVERS_MISC=y
Tom Rini9bd09622018-04-07 20:27:54 -0400[diff] [blame]18CONFIG_SPL=y
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]19CONFIG_AHCI=y
Alper Nebi Yasak2beb0f42022-01-29 18:25:30 +0300[diff] [blame]20CONFIG_REMAKE_ELF=y
Tom Rini5ca768d2022-01-24 21:08:41 +0000[diff] [blame]21CONFIG_MP=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]22CONFIG_FIT_VERBOSE=y
23CONFIG_OF_BOARD_SETUP=y
24CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rini8c70baa2021-12-14 13:36:40 -0500[diff] [blame]25CONFIG_DYNAMIC_SYS_CLK_FREQ=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]26CONFIG_SD_BOOT=y
27CONFIG_BOOTDELAY=10
Sam Protsenkobd7bffe2017-08-14 20:22:17 +0300[diff] [blame]28CONFIG_USE_BOOTARGS=y
29CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]30CONFIG_BOOTCOMMAND="mmc read 0x80200000 0x6800 0x800; fsl_mc apply dpl 0x80200000 && mmc read $kernel_load $kernel_start $kernel_size && bootm $kernel_load"
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]31CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
32CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]33CONFIG_SPL_ENV_SUPPORT=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]34CONFIG_SPL_I2C=y
Simon Glass64571062021-08-08 12:20:16 -0600[diff] [blame]35CONFIG_SPL_MPC8XXX_INIT_DDR=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]36CONFIG_CMD_GREPENV=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]37CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]38CONFIG_CMD_I2C=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]39CONFIG_CMD_MMC=y
Tom Rini00448d22017-07-28 21:31:42 -0400[diff] [blame]40CONFIG_CMD_NAND=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]41CONFIG_CMD_PCI=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]42CONFIG_CMD_USB=y
43# CONFIG_CMD_SETEXPR is not set
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]44CONFIG_CMD_CACHE=y
45CONFIG_CMD_DATE=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]46CONFIG_OF_CONTROL=y
47CONFIG_OF_EMBED=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]48CONFIG_ENV_OVERWRITE=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]49CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]50CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Tom Rinife586752022-03-11 09:12:07 -0500[diff] [blame^]51CONFIG_USE_ETHPRIME=y
52CONFIG_ETHPRIME="DPMAC1@xgmii"
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]53CONFIG_NET_RANDOM_ETHADDR=y
54CONFIG_DM=y
Simon Glass701ef062022-01-31 07:49:33 -0700[diff] [blame]55CONFIG_SATA=y
Peng Ma1c4bf2f2019-01-30 19:17:44 +0800[diff] [blame]56CONFIG_SATA_CEVA=y
Tom Rinif7246c22021-08-21 13:50:17 -0400[diff] [blame]57CONFIG_DYNAMIC_DDR_CLK_FREQ=y
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]58CONFIG_DDR_ECC=y
59CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
Tom Rini52b2e262021-08-18 23:12:24 -0400[diff] [blame]60CONFIG_SYS_I2C_LEGACY=y
Tom Rini714482a2021-08-18 23:12:25 -0400[diff] [blame]61CONFIG_SYS_I2C_EARLY_INIT=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]62CONFIG_SYS_I2C_EEPROM_ADDR=0x57
Mario Six41d7d972018-03-28 14:38:19 +0200[diff] [blame]63CONFIG_FSL_ESDHC=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]64CONFIG_MTD=y
65CONFIG_MTD_RAW_NAND=y
Tom Rinia73788c2021-09-22 14:50:37 -0400[diff] [blame]66CONFIG_NAND_FSL_IFC=y
Tom Rinifdae0072021-09-22 14:50:34 -0400[diff] [blame]67CONFIG_SYS_NAND_ONFI_DETECTION=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]68CONFIG_DM_SPI_FLASH=y
Rajat Srivastava36f09912019-04-24 18:15:12 +0530[diff] [blame]69# CONFIG_SPI_FLASH_BAR is not set
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]70CONFIG_SPI_FLASH_SPANSION=y
Alexandru Gagniucd83e98c2017-08-01 17:19:59 -0700[diff] [blame]71CONFIG_PHYLIB=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]72CONFIG_PHYLIB_10G=y
73CONFIG_PHY_REALTEK=y
74CONFIG_PHY_TERANETICS=y
75CONFIG_PHY_VITESSE=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]76CONFIG_PHY_GIGE=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]77CONFIG_E1000=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]78CONFIG_MII=y
Mark Kettenisf8463d62022-01-22 20:38:11 +0100[diff] [blame]79CONFIG_NVME_PCI=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]80CONFIG_PCI=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]81CONFIG_DM_PCI_COMPAT=y
Hou Zhiqiang02f1f062020-07-09 23:31:42 +0800[diff] [blame]82CONFIG_PCIE_LAYERSCAPE_RC=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]83CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y
Peng Ma1c4bf2f2019-01-30 19:17:44 +0800[diff] [blame]84CONFIG_DM_SCSI=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]85CONFIG_SYS_NS16550=y
Adam Ford4e96ff82018-04-15 13:51:26 -0400[diff] [blame]86CONFIG_SPI=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]87CONFIG_DM_SPI=y
88CONFIG_FSL_QSPI=y
89CONFIG_USB=y
Santan Kumar1afa9002017-05-05 15:42:29 +0530[diff] [blame]90CONFIG_USB_XHCI_HCD=y
91CONFIG_USB_XHCI_DWC3=y