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git01.mediatek.com / filogic / uboot / fe505c7538613c74893ec9a267185a34a23b112c / . / configs / chromebook_speedy_defconfig
blob: 7fc505ee4e36905f28299081a365dae25123abcb [file] [log] [blame]
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
Tom Rinid391d8b2021-12-11 14:55:51 -0500[diff] [blame]3CONFIG_SYS_ARCH_TIMER=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]4# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]5CONFIG_ARCH_ROCKCHIP=y
6CONFIG_SYS_TEXT_BASE=0x00100000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]9CONFIG_SPL_TEXT_BASE=0xff704000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]10CONFIG_ROCKCHIP_RK3288=y
Simon Glassb58bfe02021-08-08 12:20:09 -0600[diff] [blame]11# CONFIG_SPL_MMC is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]12CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]13CONFIG_SPL_STACK_R_ADDR=0x80000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]14CONFIG_DEBUG_UART_BASE=0xff690000
15CONFIG_DEBUG_UART_CLOCK=24000000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]16CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassa5820472021-08-08 12:20:14 -0600[diff] [blame]17CONFIG_SPL_SPI=y
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]18CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]19CONFIG_SPL_PAYLOAD="u-boot.img"
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]20CONFIG_DEBUG_UART=y
Tom Rini4ddbade2022-05-25 12:16:03 -0400[diff] [blame]21CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
22CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]23CONFIG_USE_PREBOOT=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]24CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
Tom Rinif92b6fa2020-10-09 12:22:06 -0400[diff] [blame]25CONFIG_SILENT_CONSOLE=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]26# CONFIG_DISPLAY_CPUINFO is not set
27CONFIG_DISPLAY_BOARDINFO_LATE=y
Urja Rannikkoe8c4c962020-05-13 19:15:21 +0000[diff] [blame]28CONFIG_BOARD_EARLY_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]29CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini0cb89e72022-05-19 15:09:22 -0400[diff] [blame]30CONFIG_SPL_NO_BSS_LIMIT=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]31# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]32# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
33CONFIG_SPL_STACK=0xff718000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]34CONFIG_SPL_STACK_R=y
35CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]36# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
Simon Glassefc12232021-07-14 17:05:32 -0500[diff] [blame]37# CONFIG_SPL_CRC32 is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]38CONFIG_SPL_SPI_LOAD=y
Tom Rinie22fa4f2021-08-10 15:08:46 -0400[diff] [blame]39CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]40CONFIG_CMD_GPIO=y
41CONFIG_CMD_GPT=y
42CONFIG_CMD_I2C=y
43CONFIG_CMD_MMC=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]44CONFIG_CMD_SF_TEST=y
45CONFIG_CMD_SPI=y
46CONFIG_CMD_USB=y
47# CONFIG_CMD_SETEXPR is not set
48CONFIG_CMD_CACHE=y
49CONFIG_CMD_TIME=y
50CONFIG_CMD_PMIC=y
51CONFIG_CMD_REGULATOR=y
52# CONFIG_SPL_DOS_PARTITION is not set
53# CONFIG_SPL_EFI_PARTITION is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]54CONFIG_SPL_OF_CONTROL=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]55CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
56CONFIG_SPL_OF_PLATDATA=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]57CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]58CONFIG_REGMAP=y
59CONFIG_SPL_REGMAP=y
60CONFIG_SYSCON=y
61CONFIG_SPL_SYSCON=y
62# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]63# CONFIG_SPL_BLK is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]64CONFIG_CLK=y
65CONFIG_SPL_CLK=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]66CONFIG_ROCKCHIP_GPIO=y
67CONFIG_I2C_CROS_EC_TUNNEL=y
68CONFIG_SYS_I2C_ROCKCHIP=y
69CONFIG_I2C_MUX=y
70CONFIG_DM_KEYBOARD=y
Simon Glass278efc682021-11-24 09:26:44 -0700[diff] [blame]71CONFIG_KEYBOARD=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]72CONFIG_CROS_EC_KEYB=y
73CONFIG_CROS_EC=y
74CONFIG_CROS_EC_SPI=y
75CONFIG_PWRSEQ=y
Jaehoon Chunge711c972021-02-16 10:16:56 +0900[diff] [blame]76CONFIG_MMC_PWRSEQ=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]77# CONFIG_SPL_DM_MMC is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]78CONFIG_MMC_DW=y
79CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]80CONFIG_MTD=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]81CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]82CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko7a19eec2019-05-13 13:51:03 +0000[diff] [blame]83CONFIG_SPI_FLASH_GIGADEVICE=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]84CONFIG_PINCTRL=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]85CONFIG_PINCONF=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]86CONFIG_SPL_PINCTRL=y
Urja Rannikkoaa02ec02020-05-13 19:15:23 +0000[diff] [blame]87# CONFIG_SPL_PINCTRL_FULL is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]88CONFIG_DM_PMIC=y
89# CONFIG_SPL_PMIC_CHILDREN is not set
90CONFIG_PMIC_RK8XX=y
91CONFIG_DM_REGULATOR_FIXED=y
92CONFIG_REGULATOR_RK8XX=y
93CONFIG_PWM_ROCKCHIP=y
94CONFIG_RAM=y
95CONFIG_SPL_RAM=y
96CONFIG_DEBUG_UART_SHIFT=2
97CONFIG_ROCKCHIP_SERIAL=y
98CONFIG_ROCKCHIP_SPI=y
99CONFIG_SYSRESET=y
100CONFIG_USB=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]101# CONFIG_SPL_DM_USB is not set
102CONFIG_USB_DWC2=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]103CONFIG_ROCKCHIP_USB2_PHY=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]104CONFIG_DM_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]105# CONFIG_VIDEO_BPP8 is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]106CONFIG_CONSOLE_TRUETYPE=y
107CONFIG_DISPLAY=y
108CONFIG_VIDEO_ROCKCHIP=y
109CONFIG_DISPLAY_ROCKCHIP_EDP=y
110CONFIG_DISPLAY_ROCKCHIP_HDMI=y
111# CONFIG_USE_PRIVATE_LIBGCC is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]112CONFIG_SPL_TINY_MEMSET=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]113CONFIG_CMD_DHRYSTONE=y
114CONFIG_ERRNO_STR=y