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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * ML2.h: ML2 specific config options
3 *
4 * Copyright 2002 Mind NV
5 *
6 * http://www.mind.be/
7 *
8 * Author : Peter De Schrijver (p2@mind.be)
9 *
10 * Derived from : other configuration header files in this tree
11 *
12 * This software may be used and distributed according to the terms of
13 * the GNU General Public License (GPL) version 2, incorporated herein by
14 * reference. Drivers based on or derived from this code fall under the GPL
15 * and must retain the authorship, copyright and this license notice. This
16 * file is not a complete program and may only be used when the entire
17 * program is licensed under the GPL.
18 *
19 */
20
21#ifndef __CONFIG_H
22#define __CONFIG_H
23
24/*
25 * High Level Configuration Options
26 * (easy to change)
27 */
28
29#define CONFIG_405 1 /* This is a PPC405 CPU */
30#define CONFIG_4xx 1 /* ...member of PPC4xx family */
31#define CONFIG_ML2 1 /* ...on a ML2 board */
32
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020033#define CONFIG_SYS_TEXT_BASE 0x18000000
wdenkfe8c2802002-11-03 00:38:21 +000034
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020035#define CONFIG_ENV_IS_IN_FLASH 1
wdenkfe8c2802002-11-03 00:38:21 +000036
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +020037#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020038#undef CONFIG_ENV_IS_IN_FLASH
wdenkfe8c2802002-11-03 00:38:21 +000039#else
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020040#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +020041#undef CONFIG_ENV_IS_IN_NVRAM
wdenkfe8c2802002-11-03 00:38:21 +000042#endif
43#endif
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#if 1
49#define CONFIG_BOOTCOMMAND "bootm" /* autoboot command */
50#else
51#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
52#endif
53
54#define CONFIG_PREBOOT "fsload 0x00100000 /boot/image"
55
wdenkfe8c2802002-11-03 00:38:21 +000056#if 0
57#define CONFIG_BOOTARGS "root=/dev/nfs " \
58 "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
59 "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
60#else
61#define CONFIG_BOOTARGS "root=/dev/mtdblock2 " \
62 "console=ttyS0 console=tty"
63
64#endif
65
66#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020067#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkfe8c2802002-11-03 00:38:21 +000068
69
Jon Loeliger446e1f52007-07-08 14:14:17 -050070/*
Jon Loeligered26c742007-07-10 09:10:49 -050071 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78
79/*
Jon Loeliger446e1f52007-07-08 14:14:17 -050080 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#define CONFIG_CMD_IRQ
85#define CONFIG_CMD_KGDB
86#define CONFIG_CMD_BEDBUG
87#define CONFIG_CMD_ELF
88#define CONFIG_CMD_JFFS2
89
90#undef CONFIG_CMD_NET
Wolfgang Denkfe33e6e2010-11-21 20:55:42 +010091#undef CONFIG_CMD_NFS
Jon Loeliger446e1f52007-07-08 14:14:17 -050092#undef CONFIG_CMD_RTC
93#undef CONFIG_CMD_PCI
94#undef CONFIG_CMD_I2C
wdenkfe8c2802002-11-03 00:38:21 +000095
wdenkfe8c2802002-11-03 00:38:21 +000096
97#undef CONFIG_WATCHDOG /* watchdog disabled */
98
99#define CONFIG_SYS_CLK_FREQ 50000000
100
101#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
102
103/*
Wolfgang Denkfe33e6e2010-11-21 20:55:42 +0100104 * I2C
105 */
106#define CONFIG_HARD_I2C /* I2C with hardware support */
107#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
108#define CONFIG_SYS_I2C_SLAVE 0x7F
109#define CONFIG_SYS_I2C_SPEED 400000
110
111/*
wdenkfe8c2802002-11-03 00:38:21 +0000112 * Miscellaneous configurable options
113 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
115#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger446e1f52007-07-08 14:14:17 -0500116#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000118#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000120#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
122#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
123#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000124
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
126#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkfe8c2802002-11-03 00:38:21 +0000127
128/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
130 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
131 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
wdenkfe8c2802002-11-03 00:38:21 +0000132 * The Linux BASE_BAUD define should match this configuration.
133 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
wdenkfe8c2802002-11-03 00:38:21 +0000135 * set Linux BASE_BAUD to 403200.
136 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
138#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
wdenkfe8c2802002-11-03 00:38:21 +0000139
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#define CONFIG_SYS_BASE_BAUD (3125000*16)
141#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_BASE_BAUD
142#define CONFIG_SYS_DUART_CHAN 0
143#define CONFIG_SYS_NS16550_COM1 0xa0001003
144#define CONFIG_SYS_NS16550_COM2 0xa0011003
145#define CONFIG_SYS_NS16550_REG_SIZE -4
146#define CONFIG_SYS_NS16550 1
147#define CONFIG_SYS_INIT_CHAN1 1
148#define CONFIG_SYS_INIT_CHAN2 1
wdenkfe8c2802002-11-03 00:38:21 +0000149
150/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkfe8c2802002-11-03 00:38:21 +0000152 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
153
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
155#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkfe8c2802002-11-03 00:38:21 +0000156
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkfe8c2802002-11-03 00:38:21 +0000158
159
wdenkfe8c2802002-11-03 00:38:21 +0000160/*-----------------------------------------------------------------------
161 * Start addresses for the final memory configuration
162 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkfe8c2802002-11-03 00:38:21 +0000164 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200165#define CONFIG_SYS_SDRAM_BASE 0x00000000
166#define CONFIG_SYS_FLASH_BASE 0x18000000
167#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
168#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
169#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000170
171/*
172 * For booting Linux, the board info and command line data
173 * have to be in the first 8 MB of memory, since this is
174 * the maximum mapped by the Linux kernel during initialization.
175 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000177/*-----------------------------------------------------------------------
178 * FLASH organization
179 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
181#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkfe8c2802002-11-03 00:38:21 +0000182
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
184#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkfe8c2802002-11-03 00:38:21 +0000185
186/* BEG ENVIRONNEMENT FLASH */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200187#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200188#define CONFIG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
189#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
190#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
wdenkfe8c2802002-11-03 00:38:21 +0000191#endif
192/* END ENVIRONNEMENT FLASH */
193/*-----------------------------------------------------------------------
194 * NVRAM organization
195 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
197#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
wdenkfe8c2802002-11-03 00:38:21 +0000198
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200199#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200200#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
201#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
wdenkfe8c2802002-11-03 00:38:21 +0000203#endif
wdenkfe8c2802002-11-03 00:38:21 +0000204
205/*
206 * Init Memory Controller:
207 *
208 * BR0/1 and OR0/1 (FLASH)
209 */
210
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
wdenkfe8c2802002-11-03 00:38:21 +0000212#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
213
214
215/* Configuration Port location */
216#define CONFIG_PORT_ADDR 0xF0000500
217
218/*-----------------------------------------------------------------------
219 * Definitions for initial stack pointer and data area (in DPRAM)
220 */
221
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200223#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200224#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000226
227/*-----------------------------------------------------------------------
228 * Definitions for Serial Presence Detect EEPROM address
229 * (to get SDRAM settings)
230 */
231#define SPD_EEPROM_ADDRESS 0x50
232
Jon Loeliger446e1f52007-07-08 14:14:17 -0500233#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000234#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
235#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
236#endif
237
Wolfgang Denk47f57792005-08-08 01:03:24 +0200238/*
239 * JFFS2 partitions
240 *
241 */
242/* No command line, one static partition, whole device */
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100243#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk47f57792005-08-08 01:03:24 +0200244#define CONFIG_JFFS2_DEV "nor0"
245#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
246#define CONFIG_JFFS2_PART_OFFSET 0x00080000
247
248/* mtdparts command line support */
249/* Note: fake mtd_id used, no linux mtd map file */
250/*
Stefan Roeseb1423dd2009-03-19 13:30:36 +0100251#define CONFIG_CMD_MTDPARTS
Wolfgang Denk47f57792005-08-08 01:03:24 +0200252#define MTDIDS_DEFAULT "nor0=ml2-0"
253#define MTDPARTS_DEFAULT "mtdparts=ml2-0:-@512k(jffs2)"
254*/
wdenkfe8c2802002-11-03 00:38:21 +0000255
wdenkfe8c2802002-11-03 00:38:21 +0000256#endif /* __CONFIG_H */