blob: 7871294e90d43ff3baa1ea806c1da8861217db17 [file] [log] [blame]
Hal Fengbaf555d2024-12-08 17:19:35 +08001// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2023 StarFive Technology Co., Ltd.
4 */
5
6#include "binman.dtsi"
7#include "jh7110-u-boot.dtsi"
8/ {
9 aliases {
10 spi0 = &qspi;
11 };
12
13 chosen {
14 bootph-pre-ram;
15 };
16
17 firmware {
18 spi0 = &qspi;
19 bootph-pre-ram;
20 };
21
22 config {
23 bootph-pre-ram;
24 u-boot,spl-payload-offset = <0x100000>;
25 };
26
27 memory@40000000 {
28 bootph-pre-ram;
29 };
30};
31
32&uart0 {
33 bootph-pre-ram;
34 reg-offset = <0>;
35 current-speed = <115200>;
36 clock-frequency = <24000000>;
37};
38
39&mmc0 {
40 bootph-pre-ram;
41};
42
43&mmc1 {
44 bootph-pre-ram;
45};
46
47&qspi {
48 bootph-pre-ram;
49
50 flash@0 {
51 bootph-pre-ram;
52 cdns,read-delay = <2>;
53 spi-max-frequency = <100000000>;
54 };
55};
56
57&syscrg {
58 assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
59 <&syscrg JH7110_SYSCLK_BUS_ROOT>,
60 <&syscrg JH7110_SYSCLK_PERH_ROOT>,
61 <&syscrg JH7110_SYSCLK_QSPI_REF>;
62 assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
63 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
64 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
65 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
66 assigned-clock-rates = <0>, <0>, <0>, <0>;
67};
68
69&sysgpio {
70 bootph-pre-ram;
71};
72
73&mmc0_pins {
74 bootph-pre-ram;
75 rst-pins {
76 bootph-pre-ram;
77 };
78};
79
80&mmc1_pins {
81 bootph-pre-ram;
82 clk-pins {
83 bootph-pre-ram;
84 };
85
86 mmc-pins {
87 bootph-pre-ram;
88 };
89};
90
91&i2c5_pins {
92 bootph-pre-ram;
93 i2c-pins {
94 bootph-pre-ram;
95 };
96};
97
98&i2c5 {
99 bootph-pre-ram;
100 eeprom@50 {
101 bootph-pre-ram;
102 compatible = "atmel,24c04";
103 reg = <0x50>;
104 pagesize = <16>;
105 };
106};
107
108&binman {
109 itb {
110 fit {
111 images {
Hal Fengd75a26b2024-12-08 17:19:39 +0800112 fdt-jh7110-milkv-mars {
113 description = "jh7110-milkv-mars";
Hal Fengbaf555d2024-12-08 17:19:35 +0800114 load = <0x40400000>;
115 compression = "none";
116
Hal Fengd75a26b2024-12-08 17:19:39 +0800117 blob-ext {
118 filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb";
Hal Fengbaf555d2024-12-08 17:19:35 +0800119 };
120 };
Hal Fengd75a26b2024-12-08 17:19:39 +0800121
122 fdt-jh7110-pine64-star64 {
123 description = "jh7110-pine64-star64";
124 load = <0x40400000>;
125 compression = "none";
126
127 blob-ext {
128 filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb";
129 };
130 };
131
132 fdt-jh7110-starfive-visionfive-2-v1.2a {
133 description = "jh7110-starfive-visionfive-2-v1.2a";
134 load = <0x40400000>;
135 compression = "none";
136
137 blob-ext {
138 filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
139 };
140 };
141
142 fdt-jh7110-starfive-visionfive-2-v1.3b {
143 description = "jh7110-starfive-visionfive-2-v1.3b";
144 load = <0x40400000>;
145 compression = "none";
146
147 blob-ext {
148 filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
149 };
150 };
Hal Fengbaf555d2024-12-08 17:19:35 +0800151 };
152
153 configurations {
Hal Fengd75a26b2024-12-08 17:19:39 +0800154 conf-jh7110-milkv-mars {
155 description = "jh7110-milkv-mars";
156 firmware = "opensbi";
157 loadables = "uboot";
158 fdt = "fdt-jh7110-milkv-mars";
159 };
160
161 conf-jh7110-pine64-star64 {
162 description = "jh7110-pine64-star64";
163 firmware = "opensbi";
164 loadables = "uboot";
165 fdt = "fdt-jh7110-pine64-star64";
166 };
167
168 conf-jh7110-starfive-visionfive-2-v1.2a {
169 description = "jh7110-starfive-visionfive-2-v1.2a";
170 firmware = "opensbi";
171 loadables = "uboot";
172 fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a";
173 };
174
175 conf-jh7110-starfive-visionfive-2-v1.3b {
176 description = "jh7110-starfive-visionfive-2-v1.3b";
177 firmware = "opensbi";
178 loadables = "uboot";
179 fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b";
Hal Fengbaf555d2024-12-08 17:19:35 +0800180 };
181 };
182 };
183 };
184
185 spl-img {
186 filename = "spl/u-boot-spl.bin.normal.out";
187
188 mkimage {
189 args = "-T sfspl";
190
191 u-boot-spl {
192 };
193 };
194 };
195};