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git01.mediatek.com / filogic / uboot / fe07df51958f7a5051a05fa6a90c293a8839f20f / . / arch / arm / dts / imxrt1170-evk.dts
blob: 0d8e70168604c8633653be7a21600026ce39cc08 [file] [log] [blame]
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2022
4 * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
5 * Giulio Benetti <giulio.benetti@benettiengineering.com>
6 */
7
8/dts-v1/;
9#include "imxrt1170.dtsi"
10#include "imxrt1170-evk-u-boot.dtsi"
11#include "imxrt1170-pinfunc.h"
12
13/ {
14 model = "NXP imxrt1170-evk board";
15 compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
16
17 chosen {
18 stdout-path = "serial0:115200n8";
19 tick-timer = &gpt1;
20 };
21
22 memory {
Jesse Taube3496bd82024-10-24 22:02:28 -0400[diff] [blame]23 #address-cells = <1>;
24 #size-cells = <1>;
Jesse Taubed68abc22022-07-26 01:43:45 -0400[diff] [blame]25 device_type = "memory";
26 reg = <0x20240000 0xf0000 0x80000000 0x4000000>;
27
28 ocram: ocram@20240000 {
29 device_type = "memory";
30 reg = <0x20240000 0xf0000>;
31 };
32
33 sdram: sdram@80000000 {
34 device_type = "memory";
35 reg = <0x80000000 0x4000000>;
36 };
37 };
38};
39
40&lpuart1 { /* console */
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_lpuart1>;
43 status = "okay";
44};
45
46&semc {
47 /*
48 * Memory configuration from sdram datasheet IS42S16160J-6BLI
49 */
50 fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
51 0
52 0
53 0
54 0
55 0>;
56 fsl,sdram-control = /bits/ 8 <MEM_WIDTH_32BITS
57 BL_8
58 COL_9BITS
59 CL_3>;
60 fsl,sdram-timing = /bits/ 8 <0x2
61 0x2
62 0xd
63 0x0
64 0x8
65 0x7
66
67 0x0d
68 0x0b
69 0x00
70 0x00
71
72 0x00
73 0x0A
74 0x08
75 0x09>;
76
77 bank1: bank@0 {
78 fsl,base-address = <0x80000000>;
79 fsl,memory-size = <MEM_SIZE_64M>;
80 };
81};
82
83&iomuxc {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_lpuart1>;
86
87 imxrt1170-evk {
88 pinctrl_lpuart1: lpuart1grp {
89 fsl,pins = <
90 IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1
91 IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1
92 >;
93 };
94
95 pinctrl_usdhc0: usdhc0grp {
96 fsl,pins = <
97 IOMUXC_GPIO_AD_32_USDHC1_CD_B
98 0x1B000
99 IOMUXC_GPIO_AD_34_USDHC1_VSELECT
100 0xB069
101 IOMUXC_GPIO_SD_B1_00_USDHC1_CMD
102 0x17061
103 IOMUXC_GPIO_SD_B1_01_USDHC1_CLK
104 0x17061
105 IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3
106 0x17061
107 IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2
108 0x17061
109 IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1
110 0x17061
111 IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0
112 0x17061
113 >;
114 };
115 pinctrl_semc: semcgrp {
116 fsl,pins = <
117 IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00
118 8 /* SEMC_D0 */
119 IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01
120 8 /* SEMC_D1 */
121 IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02
122 8 /* SEMC_D2 */
123 IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03
124 8 /* SEMC_D3 */
125 IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04
126 8 /* SEMC_D4 */
127 IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05
128 8 /* SEMC_D5 */
129 IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06
130 8 /* SEMC_D6 */
131 IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07
132 8 /* SEMC_D7 */
133 IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
134 8 /* SEMC_DM0 */
135 IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00
136 8 /* SEMC_A0 */
137 IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01
138 8 /* SEMC_A1 */
139 IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02
140 8 /* SEMC_A2 */
141 IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03
142 8 /* SEMC_A3 */
143 IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04
144 8 /* SEMC_A4 */
145 IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05
146 8 /* SEMC_A5 */
147 IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06
148 8 /* SEMC_A6 */
149 IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07
150 8 /* SEMC_A7 */
151 IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08
152 8 /* SEMC_A8 */
153 IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09
154 8 /* SEMC_A9 */
155 IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11
156 8 /* SEMC_A11 */
157 IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12
158 8 /* SEMC_A12 */
159 IOMUXC_GPIO_EMC_B1_21_SEMC_BA0
160 8 /* SEMC_BA0 */
161 IOMUXC_GPIO_EMC_B1_22_SEMC_BA1
162 8 /* SEMC_BA1 */
163 IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10
164 8 /* SEMC_A10 */
165 IOMUXC_GPIO_EMC_B1_24_SEMC_CAS
166 8 /* SEMC_CAS */
167 IOMUXC_GPIO_EMC_B1_25_SEMC_RAS
168 8 /* SEMC_RAS */
169 IOMUXC_GPIO_EMC_B1_26_SEMC_CLK
170 8 /* SEMC_CLK */
171 IOMUXC_GPIO_EMC_B1_27_SEMC_CKE
172 8 /* SEMC_CKE */
173 IOMUXC_GPIO_EMC_B1_28_SEMC_WE
174 8 /* SEMC_WE */
175 IOMUXC_GPIO_EMC_B1_29_SEMC_CS0
176 8 /* SEMC_CS0 */
177 IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08
178 8 /* SEMC_D8 */
179 IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09
180 8 /* SEMC_D9 */
181 IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10
182 8 /* SEMC_D10 */
183 IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11
184 8 /* SEMC_D11 */
185 IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12
186 8 /* SEMC_D12 */
187 IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13
188 8 /* SEMC_D13 */
189 IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14
190 8 /* SEMC_D14 */
191 IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15
192 8 /* SEMC_D15 */
193 IOMUXC_GPIO_EMC_B1_08_SEMC_DM00
194 8 /* SEMC_DM00 */
195 IOMUXC_GPIO_EMC_B1_38_SEMC_DM01
196 8 /* SEMC_DM01 */
197 IOMUXC_GPIO_EMC_B2_08_SEMC_DM02
198 4 /* SEMC_DM02 */
199 IOMUXC_GPIO_EMC_B2_17_SEMC_DM03
200 8 /* SEMC_DM03 */
201 IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16
202 8 /* SEMC_D16 */
203 IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17
204 8 /* SEMC_D17 */
205 IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18
206 8 /* SEMC_D18 */
207 IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19
208 8 /* SEMC_D19 */
209 IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20
210 8 /* SEMC_D20 */
211 IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21
212 8 /* SEMC_D21 */
213 IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22
214 8 /* SEMC_D22 */
215 IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23
216 8 /* SEMC_D23 */
217 IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24
218 8 /* SEMC_D24 */
219 IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25
220 8 /* SEMC_D25 */
221 IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26
222 4 /* SEMC_D26 */
223 IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27
224 8 /* SEMC_D27 */
225 IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28
226 8 /* SEMC_D28 */
227 IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29
228 8 /* SEMC_D29 */
229 IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30
230 8 /* SEMC_D30 */
231 IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31
232 8 /* SEMC_D31 */
233 IOMUXC_GPIO_EMC_B1_39_SEMC_DQS
234 (IMX_PAD_SION | 8) /* SEMC_DQS */
235 >;
236 };
237 };
238};
239
240&gpt1 {
241 status = "okay";
242};
243
244&usdhc1 {
245 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
246 pinctrl-0 = <&pinctrl_usdhc0>;
247 pinctrl-1 = <&pinctrl_usdhc0>;
248 pinctrl-2 = <&pinctrl_usdhc0>;
249 pinctrl-3 = <&pinctrl_usdhc0>;
250 status = "okay";
251 broken-cd;
252};