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git01.mediatek.com / filogic / uboot / fdc7e36954a5662d409fea9310c6601be44364e3 / . / configs / chromebook_speedy_defconfig
blob: c95a9a6d71a97ee5b5e45e28e42f30a271bc5f1b [file] [log] [blame]
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]1CONFIG_ARM=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]2# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]3CONFIG_ARCH_ROCKCHIP=y
4CONFIG_SYS_TEXT_BASE=0x00100000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]5CONFIG_ROCKCHIP_RK3288=y
6# CONFIG_SPL_MMC_SUPPORT is not set
7CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]8CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rinifdc7e362019-11-11 20:04:24 -0500[diff] [blame^]9CONFIG_NR_DRAM_BANKS=1
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]10CONFIG_DEBUG_UART_BASE=0xff690000
11CONFIG_DEBUG_UART_CLOCK=24000000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]12CONFIG_SPL_SPI_FLASH_SUPPORT=y
13CONFIG_SPL_SPI_SUPPORT=y
14CONFIG_DEBUG_UART=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]15CONFIG_SPL_TEXT_BASE=0xff704000
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]16CONFIG_USE_PREBOOT=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]17CONFIG_SILENT_CONSOLE=y
18CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
19# CONFIG_DISPLAY_CPUINFO is not set
20CONFIG_DISPLAY_BOARDINFO_LATE=y
21CONFIG_BOARD_EARLY_INIT_F=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]22# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]23CONFIG_SPL_STACK_R=y
24CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]25# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
26# CONFIG_SPL_CRC32_SUPPORT is not set
27CONFIG_SPL_PAYLOAD="u-boot.img"
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]28CONFIG_SPL_SPI_LOAD=y
Hannes Schmelzer38df9972019-08-22 15:41:46 +0200[diff] [blame]29CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]30CONFIG_CMD_GPIO=y
31CONFIG_CMD_GPT=y
32CONFIG_CMD_I2C=y
33CONFIG_CMD_MMC=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]34CONFIG_CMD_SF_TEST=y
35CONFIG_CMD_SPI=y
36CONFIG_CMD_USB=y
37# CONFIG_CMD_SETEXPR is not set
38CONFIG_CMD_CACHE=y
39CONFIG_CMD_TIME=y
40CONFIG_CMD_PMIC=y
41CONFIG_CMD_REGULATOR=y
42# CONFIG_SPL_DOS_PARTITION is not set
43# CONFIG_SPL_EFI_PARTITION is not set
44CONFIG_SPL_PARTITION_UUIDS=y
45CONFIG_SPL_OF_CONTROL=y
46CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
47CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
48CONFIG_SPL_OF_PLATDATA=y
49CONFIG_REGMAP=y
50CONFIG_SPL_REGMAP=y
51CONFIG_SYSCON=y
52CONFIG_SPL_SYSCON=y
53# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]54# CONFIG_SPL_BLK is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]55CONFIG_CLK=y
56CONFIG_SPL_CLK=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]57CONFIG_ROCKCHIP_GPIO=y
58CONFIG_I2C_CROS_EC_TUNNEL=y
59CONFIG_SYS_I2C_ROCKCHIP=y
60CONFIG_I2C_MUX=y
61CONFIG_DM_KEYBOARD=y
62CONFIG_CROS_EC_KEYB=y
63CONFIG_CROS_EC=y
64CONFIG_CROS_EC_SPI=y
65CONFIG_PWRSEQ=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]66# CONFIG_SPL_DM_MMC is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]67CONFIG_MMC_DW=y
68CONFIG_MMC_DW_ROCKCHIP=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]69CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]70CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko7a19eec2019-05-13 13:51:03 +0000[diff] [blame]71CONFIG_SPI_FLASH_GIGADEVICE=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]72CONFIG_PINCTRL=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]73CONFIG_PINCONF=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]74CONFIG_SPL_PINCTRL=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]75CONFIG_DM_PMIC=y
76# CONFIG_SPL_PMIC_CHILDREN is not set
77CONFIG_PMIC_RK8XX=y
78CONFIG_DM_REGULATOR_FIXED=y
79CONFIG_REGULATOR_RK8XX=y
80CONFIG_PWM_ROCKCHIP=y
81CONFIG_RAM=y
82CONFIG_SPL_RAM=y
83CONFIG_DEBUG_UART_SHIFT=2
84CONFIG_ROCKCHIP_SERIAL=y
85CONFIG_ROCKCHIP_SPI=y
86CONFIG_SYSRESET=y
87CONFIG_USB=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]88# CONFIG_SPL_DM_USB is not set
89CONFIG_USB_DWC2=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]90CONFIG_ROCKCHIP_USB2_PHY=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]91CONFIG_DM_VIDEO=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]92# CONFIG_VIDEO_BPP8 is not set
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]93CONFIG_CONSOLE_TRUETYPE=y
94CONFIG_DISPLAY=y
95CONFIG_VIDEO_ROCKCHIP=y
96CONFIG_DISPLAY_ROCKCHIP_EDP=y
97CONFIG_DISPLAY_ROCKCHIP_HDMI=y
98# CONFIG_USE_PRIVATE_LIBGCC is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]99CONFIG_SPL_TINY_MEMSET=y
Marty E. Plummer27086982019-01-05 20:12:08 -0600[diff] [blame]100CONFIG_CMD_DHRYSTONE=y
101CONFIG_ERRNO_STR=y