Blame - configs/chromebit_mickey_defconfig - filogic/uboot

blob: 9fa9d7ac58e479d0cf18577496494ef83dfd997d [file] [log] [blame]

Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	1	CONFIG_ARM=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	2	# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	3	CONFIG_ARCH_ROCKCHIP=y
Tom Rini	07edfae	2018-02-03 12:10:38 -0500	[diff] [blame]	4	CONFIG_SYS_TEXT_BASE=0x00100000
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	5	CONFIG_ROCKCHIP_RK3288=y
Tom Rini	9834b90	2017-03-13 13:48:42 -0400	[diff] [blame]	6	# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	7	CONFIG_TARGET_CHROMEBIT_MICKEY=y
Tom Rini	c9285bf	2019-04-29 15:54:04 -0400	[diff] [blame]	8	CONFIG_NR_DRAM_BANKS=1
				9	CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rini	e0056d7	2018-06-04 11:57:37 -0400	[diff] [blame]	10	CONFIG_DEBUG_UART_BASE=0xff690000
				11	CONFIG_DEBUG_UART_CLOCK=24000000
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	12	CONFIG_SPL_SPI_FLASH_SUPPORT=y
				13	CONFIG_SPL_SPI_SUPPORT=y
Tom Rini	256aa74	2017-06-19 09:47:40 -0400	[diff] [blame]	14	CONFIG_DEBUG_UART=y
Tom Rini	527ded8	2019-09-23 11:47:37 -0400	[diff] [blame]	15	CONFIG_SPL_TEXT_BASE=0xff704000
Simon Glass	4be229d	2019-07-20 20:51:14 -0600	[diff] [blame]	16	CONFIG_USE_PREBOOT=y
Klaus Goger	2b6b4f2	2018-05-25 23:45:05 +0200	[diff] [blame]	17	CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	18	# CONFIG_DISPLAY_CPUINFO is not set
Mario Six	f705544	2018-03-28 14:38:17 +0200	[diff] [blame]	19	CONFIG_DISPLAY_BOARDINFO_LATE=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	20	# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	21	CONFIG_SPL_STACK_R=y
				22	CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	23	# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
				24	# CONFIG_SPL_CRC32_SUPPORT is not set
				25	CONFIG_SPL_PAYLOAD="u-boot.img"
Marek Vasut	e254225	2018-04-07 16:05:27 +0200	[diff] [blame]	26	CONFIG_SPL_SPI_LOAD=y
Hannes Schmelzer	38df997	2019-08-22 15:41:46 +0200	[diff] [blame]	27	CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Tom Rini	78873cd	2017-08-14 19:58:53 -0400	[diff] [blame]	28	CONFIG_CMD_GPIO=y
Patrick Delaunay	7328709	2017-01-27 11:00:42 +0100	[diff] [blame]	29	CONFIG_CMD_GPT=y
Tom Rini	78873cd	2017-08-14 19:58:53 -0400	[diff] [blame]	30	CONFIG_CMD_I2C=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	31	CONFIG_CMD_MMC=y
Simon Glass	86b1b65	2017-08-04 16:34:46 -0600	[diff] [blame]	32	CONFIG_CMD_SF_TEST=y
Tom Rini	78873cd	2017-08-14 19:58:53 -0400	[diff] [blame]	33	CONFIG_CMD_SPI=y
Eddie Cai	b3501fe	2017-12-15 08:17:13 +0800	[diff] [blame]	34	CONFIG_CMD_USB=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	35	# CONFIG_CMD_SETEXPR is not set
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	36	CONFIG_CMD_CACHE=y
				37	CONFIG_CMD_TIME=y
				38	CONFIG_CMD_PMIC=y
				39	CONFIG_CMD_REGULATOR=y
Patrick Delaunay	f7e0772	2017-01-27 11:00:37 +0100	[diff] [blame]	40	# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay	8a4f2bd	2017-01-27 11:00:41 +0100	[diff] [blame]	41	# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay	7328709	2017-01-27 11:00:42 +0100	[diff] [blame]	42	CONFIG_SPL_PARTITION_UUIDS=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	43	CONFIG_SPL_OF_CONTROL=y
Tom Rini	7406032	2018-09-03 15:26:12 -0400	[diff] [blame]	44	CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	45	CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	46	CONFIG_SPL_OF_PLATDATA=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	47	CONFIG_REGMAP=y
				48	CONFIG_SPL_REGMAP=y
				49	CONFIG_SYSCON=y
				50	CONFIG_SPL_SYSCON=y
				51	# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	52	# CONFIG_SPL_BLK is not set
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	53	CONFIG_CLK=y
				54	CONFIG_SPL_CLK=y
				55	CONFIG_ROCKCHIP_GPIO=y
				56	CONFIG_I2C_CROS_EC_TUNNEL=y
				57	CONFIG_SYS_I2C_ROCKCHIP=y
				58	CONFIG_I2C_MUX=y
Masahiro Yamada	74f09b8	2016-12-07 22:10:25 +0900	[diff] [blame]	59	CONFIG_DM_KEYBOARD=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	60	CONFIG_CROS_EC_KEYB=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	61	CONFIG_CROS_EC=y
				62	CONFIG_CROS_EC_SPI=y
				63	CONFIG_PWRSEQ=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	64	# CONFIG_SPL_DM_MMC is not set
Masahiro Yamada	7942e91	2017-01-10 13:32:04 +0900	[diff] [blame]	65	CONFIG_MMC_DW=y
Masahiro Yamada	dc607f8	2017-01-10 13:32:03 +0900	[diff] [blame]	66	CONFIG_MMC_DW_ROCKCHIP=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	67	CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay	0df8104	2019-02-27 15:20:36 +0100	[diff] [blame]	68	CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko	7a19eec	2019-05-13 13:51:03 +0000	[diff] [blame]	69	CONFIG_SPI_FLASH_GIGADEVICE=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	70	CONFIG_PINCTRL=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	71	CONFIG_PINCONF=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	72	CONFIG_SPL_PINCTRL=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	73	# CONFIG_SPL_PINMUX is not set
				74	CONFIG_SPL_PINCONF=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	75	CONFIG_DM_PMIC=y
				76	# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen	614704b	2017-05-02 14:54:52 +0800	[diff] [blame]	77	CONFIG_PMIC_RK8XX=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	78	CONFIG_SPL_DM_REGULATOR=y
				79	CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen	614704b	2017-05-02 14:54:52 +0800	[diff] [blame]	80	CONFIG_REGULATOR_RK8XX=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	81	CONFIG_PWM_ROCKCHIP=y
				82	CONFIG_RAM=y
				83	CONFIG_SPL_RAM=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	84	CONFIG_DEBUG_UART_SHIFT=2
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	85	CONFIG_ROCKCHIP_SPI=y
				86	CONFIG_SYSRESET=y
Tom Rini	504997e	2017-08-25 17:50:26 -0400	[diff] [blame]	87	CONFIG_USB=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	88	# CONFIG_SPL_DM_USB is not set
				89	CONFIG_USB_DWC2=y
Adam Ford	d4183d6	2018-01-02 10:39:52 -0600	[diff] [blame]	90	CONFIG_ROCKCHIP_USB2_PHY=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	91	CONFIG_DM_VIDEO=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	92	# CONFIG_VIDEO_BPP8 is not set
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	93	CONFIG_DISPLAY=y
				94	CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com	735ddea	2017-04-17 22:24:23 +0800	[diff] [blame]	95	CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Urja Rannikko	35bd7c6	2019-05-13 13:51:05 +0000	[diff] [blame]	96	CONFIG_SPL_TINY_MEMSET=y
Simon Glass	bf8d7bf	2016-11-13 14:22:16 -0700	[diff] [blame]	97	CONFIG_CMD_DHRYSTONE=y
				98	CONFIG_ERRNO_STR=y