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wdenk3c711762004-06-09 13:37:52 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
9 *
10 * (C) Copyright 2002
11 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#include <common.h>
33#include <arm920t.h>
34#include <lh7a40x.h>
35
36#include <asm/proc-armv/ptrace.h>
37
wdenk3c711762004-06-09 13:37:52 +000038static ulong timer_load_val = 0;
39
40/* macro to read the 16 bit timer */
41static inline ulong READ_TIMER(void)
42{
wdenk37bdfdf2004-06-10 21:55:33 +000043 lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
wdenk3c711762004-06-09 13:37:52 +000044 lh7a40x_timer_t* timer = &timers->timer1;
45
46 return (timer->value & 0x0000ffff);
47}
48
49#ifdef CONFIG_USE_IRQ
50/* enable IRQ interrupts */
51void enable_interrupts (void)
52{
53 unsigned long temp;
54 __asm__ __volatile__("mrs %0, cpsr\n"
55 "bic %0, %0, #0x80\n"
56 "msr cpsr_c, %0"
57 : "=r" (temp)
58 :
59 : "memory");
60}
61
62
63/*
64 * disable IRQ/FIQ interrupts
65 * returns true if interrupts had been enabled before we disabled them
66 */
67int disable_interrupts (void)
68{
69 unsigned long old,temp;
70 __asm__ __volatile__("mrs %0, cpsr\n"
71 "orr %1, %0, #0xc0\n"
72 "msr cpsr_c, %1"
73 : "=r" (old), "=r" (temp)
74 :
75 : "memory");
76 return (old & 0x80) == 0;
77}
78#else
79void enable_interrupts (void)
80{
81 return;
82}
83int disable_interrupts (void)
84{
85 return 0;
86}
87#endif
88
89
90void bad_mode (void)
91{
92 panic ("Resetting CPU ...\n");
93 reset_cpu (0);
94}
95
96void show_regs (struct pt_regs *regs)
97{
98 unsigned long flags;
99 const char *processor_modes[] = {
100 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
101 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
102 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
103 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
104 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
105 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
106 "UK8_32", "UK9_32", "UK10_32", "UND_32",
107 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
108 };
109
110 flags = condition_codes (regs);
111
112 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
113 "sp : %08lx ip : %08lx fp : %08lx\n",
114 instruction_pointer (regs),
115 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
116 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
117 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
118 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
119 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
120 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
121 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
122 printf ("Flags: %c%c%c%c",
123 flags & CC_N_BIT ? 'N' : 'n',
124 flags & CC_Z_BIT ? 'Z' : 'z',
125 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
126 printf (" IRQs %s FIQs %s Mode %s%s\n",
127 interrupts_enabled (regs) ? "on" : "off",
128 fast_interrupts_enabled (regs) ? "on" : "off",
129 processor_modes[processor_mode (regs)],
130 thumb_mode (regs) ? " (T)" : "");
131}
132
133void do_undefined_instruction (struct pt_regs *pt_regs)
134{
135 printf ("undefined instruction\n");
136 show_regs (pt_regs);
137 bad_mode ();
138}
139
140void do_software_interrupt (struct pt_regs *pt_regs)
141{
142 printf ("software interrupt\n");
143 show_regs (pt_regs);
144 bad_mode ();
145}
146
147void do_prefetch_abort (struct pt_regs *pt_regs)
148{
149 printf ("prefetch abort\n");
150 show_regs (pt_regs);
151 bad_mode ();
152}
153
154void do_data_abort (struct pt_regs *pt_regs)
155{
156 printf ("data abort\n");
157 show_regs (pt_regs);
158 bad_mode ();
159}
160
161void do_not_used (struct pt_regs *pt_regs)
162{
163 printf ("not used\n");
164 show_regs (pt_regs);
165 bad_mode ();
166}
167
168void do_fiq (struct pt_regs *pt_regs)
169{
170 printf ("fast interrupt request\n");
171 show_regs (pt_regs);
172 bad_mode ();
173}
174
175void do_irq (struct pt_regs *pt_regs)
176{
177 printf ("interrupt request\n");
178 show_regs (pt_regs);
179 bad_mode ();
180}
181
182static ulong timestamp;
183static ulong lastdec;
184
185int interrupt_init (void)
186{
wdenk37bdfdf2004-06-10 21:55:33 +0000187 lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
wdenk3c711762004-06-09 13:37:52 +0000188 lh7a40x_timer_t* timer = &timers->timer1;
189
190 /* a periodic timer using the 508kHz source */
191 timer->control = (TIMER_PER | TIMER_CLK508K);
192
193 if (timer_load_val == 0) {
194 /*
195 * 10ms period with 508.469kHz clock = 5084
196 */
197 timer_load_val = CFG_HZ/100;
198 }
199
200 /* load value for 10 ms timeout */
201 lastdec = timer->load = timer_load_val;
202
203 /* auto load, start timer */
204 timer->control = timer->control | TIMER_EN;
205 timestamp = 0;
206
207 return (0);
208}
209
210/*
211 * timer without interrupts
212 */
213
214void reset_timer (void)
215{
216 reset_timer_masked ();
217}
218
219ulong get_timer (ulong base)
220{
221 return (get_timer_masked() - base);
222}
223
224void set_timer (ulong t)
225{
226 timestamp = t;
227}
228
229void udelay (unsigned long usec)
230{
231 ulong tmo,tmp;
232
233 /* normalize */
234 if (usec >= 1000) {
235 tmo = usec / 1000;
236 tmo *= CFG_HZ;
237 tmo /= 1000;
238 }
239 else {
240 if (usec > 1) {
241 tmo = usec * CFG_HZ;
242 tmo /= (1000*1000);
243 }
244 else
245 tmo = 1;
246 }
247
248 /* check for rollover during this delay */
249 tmp = get_timer (0);
250 if ((tmp + tmo) < tmp )
251 reset_timer_masked(); /* timer would roll over */
252 else
253 tmo += tmp;
254
255 while (get_timer_masked () < tmo);
256}
257
258void reset_timer_masked (void)
259{
260 /* reset time */
261 lastdec = READ_TIMER();
262 timestamp = 0;
263}
264
265ulong get_timer_masked (void)
266{
267 ulong now = READ_TIMER();
268
269 if (lastdec >= now) {
270 /* normal mode */
271 timestamp += (lastdec - now);
272 } else {
273 /* we have an overflow ... */
274 timestamp += ((lastdec + timer_load_val) - now);
275 }
276 lastdec = now;
277
278 return timestamp;
279}
280
281void udelay_masked (unsigned long usec)
282{
283 ulong tmo;
wdenk7af1f9d2005-04-04 12:08:28 +0000284 ulong endtime;
285 signed long diff;
wdenk3c711762004-06-09 13:37:52 +0000286
287 /* normalize */
288 if (usec >= 1000) {
289 tmo = usec / 1000;
290 tmo *= CFG_HZ;
291 tmo /= 1000;
wdenk7af1f9d2005-04-04 12:08:28 +0000292 } else {
wdenk3c711762004-06-09 13:37:52 +0000293 if (usec > 1) {
294 tmo = usec * CFG_HZ;
295 tmo /= (1000*1000);
wdenk7af1f9d2005-04-04 12:08:28 +0000296 } else {
wdenk3c711762004-06-09 13:37:52 +0000297 tmo = 1;
wdenk7af1f9d2005-04-04 12:08:28 +0000298 }
wdenk3c711762004-06-09 13:37:52 +0000299 }
300
wdenk7af1f9d2005-04-04 12:08:28 +0000301 endtime = get_timer_masked () + tmo;
wdenk3c711762004-06-09 13:37:52 +0000302
wdenk7af1f9d2005-04-04 12:08:28 +0000303 do {
304 ulong now = get_timer_masked ();
305 diff = endtime - now;
306 } while (diff >= 0);
wdenk3c711762004-06-09 13:37:52 +0000307}
308
309/*
310 * This function is derived from PowerPC code (read timebase as long long).
311 * On ARM it just returns the timer value.
312 */
313unsigned long long get_ticks(void)
314{
315 return get_timer(0);
316}
317
318/*
319 * This function is derived from PowerPC code (timebase clock frequency).
320 * On ARM it returns the number of timer ticks per second.
321 */
322ulong get_tbclk (void)
323{
324 ulong tbclk;
325
326 tbclk = timer_load_val * 100;
327
328 return tbclk;
329}