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git01.mediatek.com / filogic / uboot / fd926669376c322b39206a763c2ef0c572d9fa02 / . / drivers / spi / cadence_qspi.h
blob: 20cceca239f8e59a95bac5620dda781c6d6003c9 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]2/*
3 * Copyright (C) 2012
4 * Altera Corporation <www.altera.com>
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]5 */
6
7#ifndef __CADENCE_QSPI_H__
8#define __CADENCE_QSPI_H__
9
Simon Goldschmidt46e56a42019-03-01 20:12:35 +0100[diff] [blame]10#include <reset.h>
11
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]12#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
13
14#define CQSPI_NO_DECODER_MAX_CS 4
15#define CQSPI_DECODER_MAX_CS 16
16#define CQSPI_READ_CAPTURE_MAX_DELAY 16
17
18struct cadence_spi_platdata {
19 unsigned int max_hz;
20 void *regbase;
21 void *ahbbase;
Jason Rush1b4df5e2018-01-23 17:13:09 -0600[diff] [blame]22 bool is_decoded_cs;
23 u32 fifo_depth;
24 u32 fifo_width;
25 u32 trigger_address;
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]26
Jason Rush1b4df5e2018-01-23 17:13:09 -0600[diff] [blame]27 /* Flash parameters */
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]28 u32 page_size;
29 u32 block_size;
30 u32 tshsl_ns;
31 u32 tsd2d_ns;
32 u32 tchsh_ns;
33 u32 tslch_ns;
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]34};
35
36struct cadence_spi_priv {
37 void *regbase;
38 void *ahbbase;
39 size_t cmd_len;
40 u8 cmd_buf[32];
41 size_t data_len;
42
43 int qspi_is_init;
44 unsigned int qspi_calibrated_hz;
45 unsigned int qspi_calibrated_cs;
Chin Liang See36431f92015-10-17 08:31:55 -0500[diff] [blame]46 unsigned int previous_hz;
Simon Goldschmidt46e56a42019-03-01 20:12:35 +0100[diff] [blame]47
48 struct reset_ctl_bulk resets;
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]49};
50
51/* Functions call declaration */
52void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
53void cadence_qspi_apb_controller_enable(void *reg_base_addr);
54void cadence_qspi_apb_controller_disable(void *reg_base_addr);
55
56int cadence_qspi_apb_command_read(void *reg_base_addr,
57 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
58int cadence_qspi_apb_command_write(void *reg_base_addr,
59 unsigned int cmdlen, const u8 *cmdbuf,
60 unsigned int txlen, const u8 *txbuf);
61
62int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
Vignesh R4ca60192016-07-06 10:20:56 +0530[diff] [blame]63 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]64int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
65 unsigned int rxlen, u8 *rxbuf);
66int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
Ley Foon Tan08987992019-02-27 13:36:14 +0800[diff] [blame]67 unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]68int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
69 unsigned int txlen, const u8 *txbuf);
70
71void cadence_qspi_apb_chipselect(void *reg_base,
72 unsigned int chip_select, unsigned int decoder_enable);
Phil Edworthyeef2edc2016-11-29 12:58:31 +0000[diff] [blame]73void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
Stefan Roese1c60fe72014-11-07 12:37:49 +0100[diff] [blame]74void cadence_qspi_apb_config_baudrate_div(void *reg_base,
75 unsigned int ref_clk_hz, unsigned int sclk_hz);
76void cadence_qspi_apb_delay(void *reg_base,
77 unsigned int ref_clk, unsigned int sclk_hz,
78 unsigned int tshsl_ns, unsigned int tsd2d_ns,
79 unsigned int tchsh_ns, unsigned int tslch_ns);
80void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
81void cadence_qspi_apb_readdata_capture(void *reg_base,
82 unsigned int bypass, unsigned int delay);
83
84#endif /* __CADENCE_QSPI_H__ */