blob: 7c274b5f9940044da9ff3783124961ea54c1ff93 [file] [log] [blame]
Tom Warren795f9d72013-01-23 14:01:01 -07001/*
Jimmy Zhang2a544db2014-01-24 10:37:36 -07002 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
Tom Warren795f9d72013-01-23 14:01:01 -07003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra SoC common clock control functions */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/clock.h>
22#include <asm/arch/tegra.h>
Stephen Warren8d1fb312015-01-19 16:25:52 -070023#include <asm/arch-tegra/ap.h>
Tom Warren795f9d72013-01-23 14:01:01 -070024#include <asm/arch-tegra/clk_rst.h>
25#include <asm/arch-tegra/timer.h>
26#include <div64.h>
27#include <fdtdec.h>
28
29/*
30 * This is our record of the current clock rate of each clock. We don't
31 * fill all of these in since we are only really interested in clocks which
32 * we use as parents.
33 */
34static unsigned pll_rate[CLOCK_ID_COUNT];
35
36/*
37 * The oscillator frequency is fixed to one of four set values. Based on this
38 * the other clocks are set up appropriately.
39 */
40static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
41 13000000,
42 19200000,
43 12000000,
44 26000000,
45};
46
47/* return 1 if a peripheral ID is in range */
48#define clock_type_id_isvalid(id) ((id) >= 0 && \
49 (id) < CLOCK_TYPE_COUNT)
50
51char pllp_valid = 1; /* PLLP is set up correctly */
52
53/* return 1 if a periphc_internal_id is in range */
54#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
55 (id) < PERIPHC_COUNT)
56
57/* number of clock outputs of a PLL */
58static const u8 pll_num_clkouts[] = {
59 1, /* PLLC */
60 1, /* PLLM */
61 4, /* PLLP */
62 1, /* PLLA */
63 0, /* PLLU */
64 0, /* PLLD */
65};
66
67int clock_get_osc_bypass(void)
68{
69 struct clk_rst_ctlr *clkrst =
70 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
71 u32 reg;
72
73 reg = readl(&clkrst->crc_osc_ctrl);
74 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
75}
76
77/* Returns a pointer to the registers of the given pll */
78static struct clk_pll *get_pll(enum clock_id clkid)
79{
80 struct clk_rst_ctlr *clkrst =
81 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
82
83 assert(clock_id_is_pll(clkid));
84 return &clkrst->crc_pll[clkid];
85}
86
87int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
88 u32 *divp, u32 *cpcon, u32 *lfcon)
89{
90 struct clk_pll *pll = get_pll(clkid);
91 u32 data;
92
93 assert(clkid != CLOCK_ID_USB);
94
95 /* Safety check, adds to code size but is small */
96 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
97 return -1;
98 data = readl(&pll->pll_base);
99 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
100 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
101 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
102 data = readl(&pll->pll_misc);
103 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
104 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
105
106 return 0;
107}
108
109unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
110 u32 divp, u32 cpcon, u32 lfcon)
111{
112 struct clk_pll *pll = get_pll(clkid);
113 u32 data;
114
115 /*
116 * We cheat by treating all PLL (except PLLU) in the same fashion.
117 * This works only because:
118 * - same fields are always mapped at same offsets, except DCCON
119 * - DCCON is always 0, doesn't conflict
120 * - M,N, P of PLLP values are ignored for PLLP
121 */
122 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
123 writel(data, &pll->pll_misc);
124
125 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
126 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
127
128 if (clkid == CLOCK_ID_USB)
129 data |= divp << PLLU_VCO_FREQ_SHIFT;
130 else
131 data |= divp << PLL_DIVP_SHIFT;
132 writel(data, &pll->pll_base);
133
134 /* calculate the stable time */
135 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
136}
137
138void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
139 unsigned divisor)
140{
141 u32 *reg = get_periph_source_reg(periph_id);
142 u32 value;
143
144 value = readl(reg);
145
Stephen Warrendf5ed452014-01-24 10:16:19 -0700146 value &= ~OUT_CLK_SOURCE_31_30_MASK;
147 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
Tom Warren795f9d72013-01-23 14:01:01 -0700148
149 value &= ~OUT_CLK_DIVISOR_MASK;
150 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
151
152 writel(value, reg);
153}
154
155void clock_ll_set_source(enum periph_id periph_id, unsigned source)
156{
157 u32 *reg = get_periph_source_reg(periph_id);
158
Stephen Warrendf5ed452014-01-24 10:16:19 -0700159 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
160 source << OUT_CLK_SOURCE_31_30_SHIFT);
Tom Warren795f9d72013-01-23 14:01:01 -0700161}
162
163/**
164 * Given the parent's rate and the required rate for the children, this works
165 * out the peripheral clock divider to use, in 7.1 binary format.
166 *
167 * @param divider_bits number of divider bits (8 or 16)
168 * @param parent_rate clock rate of parent clock in Hz
169 * @param rate required clock rate for this clock
170 * @return divider which should be used
171 */
172static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
173 unsigned long rate)
174{
175 u64 divider = parent_rate * 2;
176 unsigned max_divider = 1 << divider_bits;
177
178 divider += rate - 1;
179 do_div(divider, rate);
180
181 if ((s64)divider - 2 < 0)
182 return 0;
183
184 if ((s64)divider - 2 >= max_divider)
185 return -1;
186
187 return divider - 2;
188}
189
190int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
191{
192 struct clk_pll *pll = get_pll(clkid);
193 int data = 0, div = 0, offset = 0;
194
195 if (!clock_id_is_pll(clkid))
196 return -1;
197
198 if (pllout + 1 > pll_num_clkouts[clkid])
199 return -1;
200
201 div = clk_get_divider(8, pll_rate[clkid], rate);
202
203 if (div < 0)
204 return -1;
205
206 /* out2 and out4 are in the high part of the register */
207 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
208 offset = 16;
209
210 data = (div << PLL_OUT_RATIO_SHIFT) |
211 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
212 clrsetbits_le32(&pll->pll_out[pllout >> 1],
213 PLL_OUT_RATIO_MASK << offset, data << offset);
214
215 return 0;
216}
217
218/**
219 * Given the parent's rate and the divider in 7.1 format, this works out the
220 * resulting peripheral clock rate.
221 *
222 * @param parent_rate clock rate of parent clock in Hz
223 * @param divider which should be used in 7.1 format
224 * @return effective clock rate of peripheral
225 */
226static unsigned long get_rate_from_divider(unsigned long parent_rate,
227 int divider)
228{
229 u64 rate;
230
231 rate = (u64)parent_rate * 2;
232 do_div(rate, divider + 2);
233 return rate;
234}
235
236unsigned long clock_get_periph_rate(enum periph_id periph_id,
237 enum clock_id parent)
238{
239 u32 *reg = get_periph_source_reg(periph_id);
240
241 return get_rate_from_divider(pll_rate[parent],
242 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
243}
244
245/**
246 * Find the best available 7.1 format divisor given a parent clock rate and
247 * required child clock rate. This function assumes that a second-stage
248 * divisor is available which can divide by powers of 2 from 1 to 256.
249 *
250 * @param divider_bits number of divider bits (8 or 16)
251 * @param parent_rate clock rate of parent clock in Hz
252 * @param rate required clock rate for this clock
253 * @param extra_div value for the second-stage divisor (not set if this
254 * function returns -1.
255 * @return divider which should be used, or -1 if nothing is valid
256 *
257 */
258static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
259 unsigned long rate, int *extra_div)
260{
261 int shift;
262 int best_divider = -1;
263 int best_error = rate;
264
265 /* try dividers from 1 to 256 and find closest match */
266 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
267 unsigned divided_parent = parent_rate >> shift;
268 int divider = clk_get_divider(divider_bits, divided_parent,
269 rate);
270 unsigned effective_rate = get_rate_from_divider(divided_parent,
271 divider);
272 int error = rate - effective_rate;
273
274 /* Given a valid divider, look for the lowest error */
275 if (divider != -1 && error < best_error) {
276 best_error = error;
277 *extra_div = 1 << shift;
278 best_divider = divider;
279 }
280 }
281
282 /* return what we found - *extra_div will already be set */
283 return best_divider;
284}
285
286/**
287 * Adjust peripheral PLL to use the given divider and source.
288 *
289 * @param periph_id peripheral to adjust
290 * @param source Source number (0-3 or 0-7)
291 * @param mux_bits Number of mux bits (2 or 4)
292 * @param divider Required divider in 7.1 or 15.1 format
293 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
294 * for this peripheral)
295 */
296static int adjust_periph_pll(enum periph_id periph_id, int source,
297 int mux_bits, unsigned divider)
298{
299 u32 *reg = get_periph_source_reg(periph_id);
300
301 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
302 divider << OUT_CLK_DIVISOR_SHIFT);
303 udelay(1);
304
305 /* work out the source clock and set it */
306 if (source < 0)
307 return -1;
Tom Warren2fde44e2014-01-24 10:16:22 -0700308
309 switch (mux_bits) {
310 case MASK_BITS_31_30:
Stephen Warrendf5ed452014-01-24 10:16:19 -0700311 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
312 source << OUT_CLK_SOURCE_31_30_SHIFT);
Tom Warren2fde44e2014-01-24 10:16:22 -0700313 break;
314
315 case MASK_BITS_31_29:
316 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
317 source << OUT_CLK_SOURCE_31_29_SHIFT);
318 break;
319
320 case MASK_BITS_31_28:
321 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
322 source << OUT_CLK_SOURCE_31_28_SHIFT);
323 break;
324
325 default:
326 return -1;
Tom Warren795f9d72013-01-23 14:01:01 -0700327 }
Tom Warren2fde44e2014-01-24 10:16:22 -0700328
Tom Warren795f9d72013-01-23 14:01:01 -0700329 udelay(2);
330 return 0;
331}
332
333unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
334 enum clock_id parent, unsigned rate, int *extra_div)
335{
336 unsigned effective_rate;
337 int mux_bits, divider_bits, source;
338 int divider;
Allen Martin810a4e42013-05-10 16:56:55 +0000339 int xdiv = 0;
Tom Warren795f9d72013-01-23 14:01:01 -0700340
341 /* work out the source clock and set it */
342 source = get_periph_clock_source(periph_id, parent, &mux_bits,
343 &divider_bits);
344
Allen Martin810a4e42013-05-10 16:56:55 +0000345 divider = find_best_divider(divider_bits, pll_rate[parent],
346 rate, &xdiv);
Tom Warren795f9d72013-01-23 14:01:01 -0700347 if (extra_div)
Allen Martin810a4e42013-05-10 16:56:55 +0000348 *extra_div = xdiv;
349
Tom Warren795f9d72013-01-23 14:01:01 -0700350 assert(divider >= 0);
351 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
352 return -1U;
353 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
354 get_periph_source_reg(periph_id),
355 readl(get_periph_source_reg(periph_id)));
356
357 /* Check what we ended up with. This shouldn't matter though */
358 effective_rate = clock_get_periph_rate(periph_id, parent);
359 if (extra_div)
360 effective_rate /= *extra_div;
361 if (rate != effective_rate)
362 debug("Requested clock rate %u not honored (got %u)\n",
363 rate, effective_rate);
364 return effective_rate;
365}
366
367unsigned clock_start_periph_pll(enum periph_id periph_id,
368 enum clock_id parent, unsigned rate)
369{
370 unsigned effective_rate;
371
372 reset_set_enable(periph_id, 1);
373 clock_enable(periph_id);
374
375 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
376 NULL);
377
378 reset_set_enable(periph_id, 0);
379 return effective_rate;
380}
381
382void clock_enable(enum periph_id clkid)
383{
384 clock_set_enable(clkid, 1);
385}
386
387void clock_disable(enum periph_id clkid)
388{
389 clock_set_enable(clkid, 0);
390}
391
392void reset_periph(enum periph_id periph_id, int us_delay)
393{
394 /* Put peripheral into reset */
395 reset_set_enable(periph_id, 1);
396 udelay(us_delay);
397
398 /* Remove reset */
399 reset_set_enable(periph_id, 0);
400
401 udelay(us_delay);
402}
403
404void reset_cmplx_set_enable(int cpu, int which, int reset)
405{
406 struct clk_rst_ctlr *clkrst =
407 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
408 u32 mask;
409
410 /* Form the mask, which depends on the cpu chosen (2 or 4) */
411 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
412 mask = which << cpu;
413
414 /* either enable or disable those reset for that CPU */
415 if (reset)
416 writel(mask, &clkrst->crc_cpu_cmplx_set);
417 else
418 writel(mask, &clkrst->crc_cpu_cmplx_clr);
419}
420
421unsigned clock_get_rate(enum clock_id clkid)
422{
423 struct clk_pll *pll;
424 u32 base;
425 u32 divm;
426 u64 parent_rate;
427 u64 rate;
428
429 parent_rate = osc_freq[clock_get_osc_freq()];
430 if (clkid == CLOCK_ID_OSC)
431 return parent_rate;
432
433 pll = get_pll(clkid);
434 base = readl(&pll->pll_base);
435
436 /* Oh for bf_unpack()... */
437 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
438 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
439 if (clkid == CLOCK_ID_USB)
440 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
441 else
442 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
443 do_div(rate, divm);
444 return rate;
445}
446
447/**
448 * Set the output frequency you want for each PLL clock.
449 * PLL output frequencies are programmed by setting their N, M and P values.
450 * The governing equations are:
451 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
452 * where Fo is the output frequency from the PLL.
453 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
454 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
455 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
456 *
457 * @param n PLL feedback divider(DIVN)
458 * @param m PLL input divider(DIVN)
459 * @param p post divider(DIVP)
460 * @param cpcon base PLL charge pump(CPCON)
461 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
462 * be overriden), 1 if PLL is already correct
463 */
464int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
465{
466 u32 base_reg;
467 u32 misc_reg;
468 struct clk_pll *pll;
469
470 pll = get_pll(clkid);
471
472 base_reg = readl(&pll->pll_base);
473
474 /* Set BYPASS, m, n and p to PLL_BASE */
475 base_reg &= ~PLL_DIVM_MASK;
476 base_reg |= m << PLL_DIVM_SHIFT;
477
478 base_reg &= ~PLL_DIVN_MASK;
479 base_reg |= n << PLL_DIVN_SHIFT;
480
481 base_reg &= ~PLL_DIVP_MASK;
482 base_reg |= p << PLL_DIVP_SHIFT;
483
484 if (clkid == CLOCK_ID_PERIPH) {
485 /*
486 * If the PLL is already set up, check that it is correct
487 * and record this info for clock_verify() to check.
488 */
489 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
490 base_reg |= PLL_ENABLE_MASK;
491 if (base_reg != readl(&pll->pll_base))
492 pllp_valid = 0;
493 return pllp_valid ? 1 : -1;
494 }
495 base_reg |= PLL_BASE_OVRRIDE_MASK;
496 }
497
498 base_reg |= PLL_BYPASS_MASK;
499 writel(base_reg, &pll->pll_base);
500
501 /* Set cpcon to PLL_MISC */
502 misc_reg = readl(&pll->pll_misc);
503 misc_reg &= ~PLL_CPCON_MASK;
504 misc_reg |= cpcon << PLL_CPCON_SHIFT;
505 writel(misc_reg, &pll->pll_misc);
506
507 /* Enable PLL */
508 base_reg |= PLL_ENABLE_MASK;
509 writel(base_reg, &pll->pll_base);
510
511 /* Disable BYPASS */
512 base_reg &= ~PLL_BYPASS_MASK;
513 writel(base_reg, &pll->pll_base);
514
515 return 0;
516}
517
518void clock_ll_start_uart(enum periph_id periph_id)
519{
520 /* Assert UART reset and enable clock */
521 reset_set_enable(periph_id, 1);
522 clock_enable(periph_id);
523 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
524
525 /* wait for 2us */
526 udelay(2);
527
528 /* De-assert reset to UART */
529 reset_set_enable(periph_id, 0);
530}
531
532#ifdef CONFIG_OF_CONTROL
533int clock_decode_periph_id(const void *blob, int node)
534{
535 enum periph_id id;
536 u32 cell[2];
537 int err;
538
539 err = fdtdec_get_int_array(blob, node, "clocks", cell,
540 ARRAY_SIZE(cell));
541 if (err)
542 return -1;
543 id = clk_id_to_periph_id(cell[1]);
544 assert(clock_periph_id_isvalid(id));
545 return id;
546}
547#endif /* CONFIG_OF_CONTROL */
548
549int clock_verify(void)
550{
551 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
552 u32 reg = readl(&pll->pll_base);
553
554 if (!pllp_valid) {
555 printf("Warning: PLLP %x is not correct\n", reg);
556 return -1;
557 }
558 debug("PLLP %x is correct\n", reg);
559 return 0;
560}
561
562void clock_init(void)
563{
564 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
565 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
566 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
567 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
568 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
569 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
570 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
571 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
572 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
573 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
574 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
Tom Warrenfbef3552013-04-01 15:48:54 -0700575
576 /* Do any special system timer/TSC setup */
Stephen Warren8d1fb312015-01-19 16:25:52 -0700577#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
578 if (!tegra_cpu_is_non_secure())
579#endif
580 arch_timer_init();
Tom Warren795f9d72013-01-23 14:01:01 -0700581}
Jimmy Zhang2a544db2014-01-24 10:37:36 -0700582
583static void set_avp_clock_source(u32 src)
584{
585 struct clk_rst_ctlr *clkrst =
586 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
587 u32 val;
588
589 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
590 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
591 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
592 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
593 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
594 writel(val, &clkrst->crc_sclk_brst_pol);
595 udelay(3);
596}
597
598/*
599 * This function is useful on Tegra30, and any later SoCs that have compatible
600 * PLLP configuration registers.
601 */
602void tegra30_set_up_pllp(void)
603{
604 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
605 u32 reg;
606
607 /*
608 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
609 * run up to 275MHz. On power on, the default sytem clock source is set
610 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
611 * 408MHz which is beyond system clock's upper limit.
612 *
613 * The fix is to set the system clock to CLK_M before initializing PLLP,
614 * and then switch back to PLLP_OUT4, which has an appropriate divider
615 * configured, after PLLP has been configured
616 */
617 set_avp_clock_source(SCLK_SOURCE_CLKM);
618
619 /*
620 * PLLP output frequency set to 408Mhz
621 * PLLC output frequency set to 228Mhz
622 */
623 switch (clock_get_osc_freq()) {
624 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
625 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
626 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
627 break;
628
629 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
630 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
631 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
632 break;
633
634 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
635 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
636 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
637 break;
638 case CLOCK_OSC_FREQ_19_2:
639 default:
640 /*
641 * These are not supported. It is too early to print a
642 * message and the UART likely won't work anyway due to the
643 * oscillator being wrong.
644 */
645 break;
646 }
647
648 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
649
650 /* OUT1, 2 */
651 /* Assert RSTN before enable */
652 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
653 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
654 /* Set divisor and reenable */
655 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
656 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
657 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
658 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
659 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
660
661 /* OUT3, 4 */
662 /* Assert RSTN before enable */
663 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
664 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
665 /* Set divisor and reenable */
666 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
667 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
668 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
669 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
670 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
671
672 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
673}