Blame - board/ttcontrol/vision2/imximage_hynix.cfg - filogic/uboot

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Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	1	/*
				2	* (C) Copyright 2009
				3	* Stefano Babic DENX Software Engineering sbabic@denx.de.
				4	*
				5	* (C) Copyright 2010
				6	* Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
				7	*
Wolfgang Denk	d79de1d	2013-07-08 09:37:19 +0200	[diff] [blame]	8	* SPDX-License-Identifier: GPL-2.0+
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	9	*
Anatolij Gustschin	fd4b3d3	2013-04-30 11:15:33 +0000	[diff] [blame]	10	* Refer doc/README.imximage for more details about how-to configure
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	11	* and create imximage boot image
				12	*
				13	* The syntax is taken as close as possible with the kwbimage
				14	*/
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	15
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	16	/*
				17	* Boot Device : one of
				18	* spi, nand, onenand, sd
				19	*/
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	20	BOOT_FROM spi
				21
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	22	/*
				23	* Device Configuration Data (DCD)
				24	*
				25	* Each entry must have the format:
				26	* Addr-type Address Value
				27	*
				28	* where:
				29	* Addr-type register length (1,2 or 4 bytes)
				30	* Address absolute address of the register
				31	* value value to be stored in the register
				32	*/
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	33
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	34	/*
				35	* #######################
				36	* ### Disable WDOG ###
				37	* #######################
				38	*/
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	39	DATA 2 0x73f98000 0x30
				40
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	41	/*
				42	* #######################
				43	* ### SET DDR Clk ###
				44	* #######################
				45	*/
				46	/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	47	DATA 4 0x73FD4018 0x000024C0
				48
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	49	/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	50	DATA 4 0x73FD4038 0x2010241
				51
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	52	/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE \| DRV_MAX \| SRE_FAST */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	53	DATA 4 0x73fa8600 0x00000107
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	54	/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE \| DRV_MAX \| SRE_FAST */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	55	DATA 4 0x73fa8604 0x00000107
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	56	/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE \| PKE_ENABLE \| DRV_MAX \| SRE_FAST */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	57	DATA 4 0x73fa8608 0x00000187
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	58	/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE \| PKE_ENABLE \| DRV_MAX \| SRE_FAST */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	59	DATA 4 0x73fa860c 0x00000187
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	60	/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE \| DRV_MAX \| SRE_FAST */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	61	DATA 4 0x73fa8614 0x00000107
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	62	/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE \| DRV_MAX \| SRE_FAST (CSPI1_SS2) */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	63	DATA 4 0x73fa86a8 0x00000187
				64
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	65	/*
				66	* #######################
				67	* ### Settings IOMUXC ###
				68	* #######################
				69	*/
				70	/*
				71	* DDR IOMUX configuration
				72	* Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
				73	* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
				74	*/
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	75	DATA 4 0x73fa84b8 0x000000e7
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	76	/* PVTC MAX (at GPC, PGR reg) */
				77	/* DATA 4 0x73FD8004 0x1fc00000 */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	78
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	79	/* DQM0 DS high slew rate slow */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	80	DATA 4 0x73fa84d4 0x000000e4
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	81	/* DQM1 DS high slew rate slow */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	82	DATA 4 0x73fa84d8 0x000000e4
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	83	/* DQM2 DS high slew rate slow */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	84	DATA 4 0x73fa84dc 0x000000e4
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	85	/* DQM3 DS high slew rate slow */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	86	DATA 4 0x73fa84e0 0x000000e4
				87
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	88	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	89	DATA 4 0x73fa84bc 0x000000c4
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	90	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	91	DATA 4 0x73fa84c0 0x000000c4
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	92	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	93	DATA 4 0x73fa84c4 0x000000c4
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	94	/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	95	DATA 4 0x73fa84c8 0x000000c4
				96
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	97	/* DRAM_DATA B0 */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	98	DATA 4 0x73fa88a4 0x00000004
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	99	/* DRAM_DATA B1 */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	100	DATA 4 0x73fa88ac 0x00000004
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	101	/* DRAM_DATA B2 */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	102	DATA 4 0x73fa88b8 0x00000004
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	103	/* DRAM_DATA B3 */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	104	DATA 4 0x73fa882c 0x00000004
				105
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	106	/* DRAM_DATA B0 slew rate */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	107	DATA 4 0x73fa8878 0x00000000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	108	/* DRAM_DATA B1 slew rate */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	109	DATA 4 0x73fa8880 0x00000000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	110	/* DRAM_DATA B2 slew rate */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	111	DATA 4 0x73fa888c 0x00000000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	112	/* DRAM_DATA B3 slew rate */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	113	DATA 4 0x73fa889c 0x00000000
				114
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	115	/*
				116	* #######################
				117	* ### Configure SDRAM ###
				118	* #######################
				119	*/
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	120
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	121	/* Configure CS0 */
				122	/* ####################### */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	123
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	124	/* ESDCTL0: Enable controller */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	125	DATA 4 0x83fd9000 0x83220000
				126
Jeroen Hofstee	0f0850e	2014-06-10 23:16:09 +0200	[diff] [blame]	127	/* Init DRAM on CS0 */
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	128	/* ESDSCR: Precharge command */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	129	DATA 4 0x83fd9014 0x04008008
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	130	/* ESDSCR: Refresh command */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	131	DATA 4 0x83fd9014 0x00008010
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	132	/* ESDSCR: Refresh command */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	133	DATA 4 0x83fd9014 0x00008010
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	134	/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	135	DATA 4 0x83fd9014 0x00338018
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	136	/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	137	DATA 4 0x83fd9014 0x0020801a
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	138	/* ESDSCR */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	139	DATA 4 0x83fd9014 0x00008000
				140
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	141	/* ESDSCR: EMR with full Drive strength */
				142	/* DATA 4 0x83fd9014 0x0000801a */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	143
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	144	/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	145	DATA 4 0x83fd9000 0xC3220000
				146
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	147	/*
				148	* ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
				149	* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
				150	* DATA 4 0x83fd9004 0xC33574AA
				151	*/
				152	/*
				153	* micron mDDR
				154	* ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
				155	* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
				156	* DATA 4 0x83FD9004 0x101564a8
				157	*/
				158	/*
				159	* hynix mDDR
				160	* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
				161	* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
				162	*/
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	163	DATA 4 0x83FD9004 0x704564a8
				164
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	165	/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	166	DATA 4 0x83fd9010 0x000a1700
				167
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	168	/* Configure CS1 */
				169	/* ####################### */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	170
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	171	/* ESDCTL1: Enable controller */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	172	DATA 4 0x83fd9008 0x83220000
				173
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	174	/* Init DRAM on CS1 */
				175	/* ESDSCR: Precharge command */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	176	DATA 4 0x83fd9014 0x0400800c
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	177	/* ESDSCR: Refresh command */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	178	DATA 4 0x83fd9014 0x00008014
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	179	/* ESDSCR: Refresh command */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	180	DATA 4 0x83fd9014 0x00008014
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	181	/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	182	DATA 4 0x83fd9014 0x0033801c
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	183	/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	184	DATA 4 0x83fd9014 0x0020801e
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	185	/* ESDSCR */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	186	DATA 4 0x83fd9014 0x00008004
				187
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	188	/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	189	DATA 4 0x83fd9008 0xC3220000
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	190	/*
				191	* ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
				192	* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
				193	* DATA 4 0x83fd900c 0xC33574AA
				194	*/
				195	/*
				196	* micron mDDR
				197	* ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
				198	* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
				199	* DATA 4 0x83FD900C 0x101564a8
				200	*/
				201	/*
				202	* hynix mDDR
				203	* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
				204	* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
				205	*/
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	206	DATA 4 0x83FD900C 0x704564a8
				207
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	208	/* ESDSCR (mDRAM configuration finished) */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	209	DATA 4 0x83FD9014 0x00000004
				210
Troy Kisky	a18d786	2013-01-18 16:14:24 +0000	[diff] [blame]	211	/* ESDSCR - clear "configuration request" bit */
Stefano Babic	e1b6f59	2010-07-06 19:32:09 +0200	[diff] [blame]	212	DATA 4 0x83fd9014 0x00000000