Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Device Tree Source extras for U-Boot for the GR Peach board |
| 4 | * |
| 5 | * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> |
| 6 | */ |
| 7 | |
Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 8 | |
| 9 | / { |
| 10 | aliases { |
| 11 | spi0 = &rpc; |
| 12 | }; |
| 13 | |
| 14 | soc { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 15 | bootph-all; |
Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 16 | }; |
| 17 | |
| 18 | leds { |
| 19 | led1 { |
| 20 | label = "peach:bottom:red"; |
| 21 | }; |
| 22 | |
| 23 | led-red { |
| 24 | label = "peach:tri:red"; |
| 25 | gpios = <&port6 13 GPIO_ACTIVE_HIGH>; |
| 26 | }; |
| 27 | |
| 28 | led-green { |
| 29 | label = "peach:tri:green"; |
| 30 | gpios = <&port6 14 GPIO_ACTIVE_HIGH>; |
| 31 | }; |
| 32 | |
| 33 | led-blue { |
| 34 | label = "peach:tri:blue"; |
| 35 | gpios = <&port6 15 GPIO_ACTIVE_HIGH>; |
| 36 | }; |
| 37 | }; |
| 38 | |
Marek Vasut | 4c5fee0 | 2019-08-11 13:22:32 +0200 | [diff] [blame] | 39 | reg_usbhs0_vbus: regulator-usbhs0-vbus { |
| 40 | compatible = "regulator-fixed"; |
| 41 | regulator-name = "usbhs0_vbus"; |
| 42 | regulator-min-microvolt = <5000000>; |
| 43 | regulator-max-microvolt = <5000000>; |
| 44 | gpio = <&port4 1 GPIO_ACTIVE_LOW>; |
| 45 | }; |
| 46 | |
| 47 | |
Geert Uytterhoeven | 6bf8365 | 2022-03-29 14:19:07 +0200 | [diff] [blame] | 48 | rpc: spi@ee200000 { |
Geert Uytterhoeven | 431ded6 | 2022-03-29 14:19:09 +0200 | [diff] [blame] | 49 | compatible = "renesas,r7s72100-rpc-if"; |
Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 50 | reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>; |
| 51 | bank-width = <2>; |
| 52 | num-cs = <1>; |
| 53 | status = "okay"; |
| 54 | spi-max-frequency = <50000000>; |
| 55 | #address-cells = <1>; |
| 56 | #size-cells = <0>; |
| 57 | |
| 58 | flash0: spi-flash@0 { |
| 59 | #address-cells = <1>; |
| 60 | #size-cells = <1>; |
| 61 | compatible = "jedec,spi-nor"; |
| 62 | spi-max-frequency = <50000000>; |
| 63 | spi-tx-bus-width = <1>; |
| 64 | spi-rx-bus-width = <1>; |
| 65 | reg = <0>; |
| 66 | status = "okay"; |
| 67 | }; |
| 68 | }; |
| 69 | }; |
| 70 | |
| 71 | &ostm0 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 72 | bootph-all; |
Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | &pinctrl { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 76 | bootph-all; |
Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 77 | }; |
| 78 | |
| 79 | &scif2 { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 80 | bootph-all; |
Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 81 | clock = <66666666>; /* ToDo: Replace by DM clock driver */ |
| 82 | }; |
| 83 | |
| 84 | &scif2_pins { |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 85 | bootph-all; |
Chris Brandt | 1f3b667 | 2017-08-23 14:53:59 -0500 | [diff] [blame] | 86 | }; |
Marek Vasut | 4c5fee0 | 2019-08-11 13:22:32 +0200 | [diff] [blame] | 87 | |
| 88 | &usbhs0 { |
| 89 | vbus-supply = <®_usbhs0_vbus>; |
| 90 | status = "okay"; |
| 91 | }; |