blob: 34fba29e859c0a12ed47cdfa4ea56d47a65b2290 [file] [log] [blame]
Chris Brandt1f3b6672017-08-23 14:53:59 -05001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source extras for U-Boot for the GR Peach board
4 *
5 * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
6 */
7
Chris Brandt1f3b6672017-08-23 14:53:59 -05008
9/ {
10 aliases {
11 spi0 = &rpc;
12 };
13
14 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -070015 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050016 };
17
18 leds {
19 led1 {
20 label = "peach:bottom:red";
21 };
22
23 led-red {
24 label = "peach:tri:red";
25 gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
26 };
27
28 led-green {
29 label = "peach:tri:green";
30 gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
31 };
32
33 led-blue {
34 label = "peach:tri:blue";
35 gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
36 };
37 };
38
Marek Vasut4c5fee02019-08-11 13:22:32 +020039 reg_usbhs0_vbus: regulator-usbhs0-vbus {
40 compatible = "regulator-fixed";
41 regulator-name = "usbhs0_vbus";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
44 gpio = <&port4 1 GPIO_ACTIVE_LOW>;
45 };
46
47
Geert Uytterhoeven6bf83652022-03-29 14:19:07 +020048 rpc: spi@ee200000 {
Geert Uytterhoeven431ded62022-03-29 14:19:09 +020049 compatible = "renesas,r7s72100-rpc-if";
Chris Brandt1f3b6672017-08-23 14:53:59 -050050 reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
51 bank-width = <2>;
52 num-cs = <1>;
53 status = "okay";
54 spi-max-frequency = <50000000>;
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 flash0: spi-flash@0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "jedec,spi-nor";
62 spi-max-frequency = <50000000>;
63 spi-tx-bus-width = <1>;
64 spi-rx-bus-width = <1>;
65 reg = <0>;
66 status = "okay";
67 };
68 };
69};
70
71&ostm0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070072 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050073};
74
75&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -070076 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050077};
78
79&scif2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070080 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050081 clock = <66666666>; /* ToDo: Replace by DM clock driver */
82};
83
84&scif2_pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -070085 bootph-all;
Chris Brandt1f3b6672017-08-23 14:53:59 -050086};
Marek Vasut4c5fee02019-08-11 13:22:32 +020087
88&usbhs0 {
89 vbus-supply = <&reg_usbhs0_vbus>;
90 status = "okay";
91};