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git01.mediatek.com / filogic / uboot / fd5c8845db8c3ce1d7cd29797cdf64ea188a8670 / . / arch / arm / dts / k3-am62a7-sk-u-boot.dtsi
blob: c42dec161940c2ec34b537f7f594f5fd3a110f93 [file] [log] [blame]
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common AM62A EVM dts file for SPLs
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]7#include "k3-am62a-sk-binman.dtsi"
8
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]12 tick-timer = &main_timer0;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]13 };
14
15 memory@80000000 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]16 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]17 };
18};
19
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]20&main_timer0 {
21 bootph-all;
22};
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]23
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]24&cbass_main {
25 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]26};
27
28&dmss {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]29 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]30};
31
32&secure_proxy_main {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]33 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]34};
35
36&dmsc {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]37 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]38};
39
40&k3_pds {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]41 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]42};
43
44&k3_clks {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]45 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]46};
47
48&k3_reset {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]49 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]50};
51
52&wkup_conf {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]53 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]54};
55
56&chipid {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]57 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]58};
59
60&main_pmx0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]61 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]62};
63
64&main_uart0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]65 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]66};
67
68&main_uart0_pins_default {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]69 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]70};
71
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]72&cbass_mcu {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]73 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]74};
75
76&cbass_wakeup {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]77 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]78};
79
80&mcu_pmx0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]81 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]82};
83
84&main_gpio0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]85 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]86};
87
88&main_i2c0 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]89 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]90};
91
92&main_i2c0_pins_default {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]93 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]94};
95
96&main_i2c1 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]97 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]98};
99
100&main_i2c1_pins_default {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]101 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]102};
103
104&exp1 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]105 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]106};
107
108&sdhci1 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]109 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]110};
111
112&main_mmc1_pins_default {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]113 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]114};
115
116&k3_reset {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]117 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]118};
119
120&dmsc {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]121 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]122};
123
124&vdd_mmc1 {
Nishanth Menonca012b92023-11-13 08:51:43 -0600[diff] [blame]125 bootph-all;
126};
127
128&main_bcdma {
129 reg = <0x00 0x485c0100 0x00 0x100>,
130 <0x00 0x4c000000 0x00 0x20000>,
131 <0x00 0x4a820000 0x00 0x20000>,
132 <0x00 0x4aa40000 0x00 0x20000>,
133 <0x00 0x4bc00000 0x00 0x100000>,
134 <0x00 0x48600000 0x00 0x8000>,
135 <0x00 0x484a4000 0x00 0x2000>,
136 <0x00 0x484c2000 0x00 0x2000>;
137 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
138 "ringrt" , "cfg", "tchan", "rchan";
139 bootph-all;
140};
141
142&main_pktdma {
143 reg = <0x00 0x485c0000 0x00 0x100>,
144 <0x00 0x4a800000 0x00 0x20000>,
145 <0x00 0x4aa00000 0x00 0x20000>,
146 <0x00 0x4b800000 0x00 0x200000>,
147 <0x00 0x485e0000 0x00 0x10000>,
148 <0x00 0x484a0000 0x00 0x2000>,
149 <0x00 0x484c0000 0x00 0x2000>,
150 <0x00 0x48430000 0x00 0x1000>;
151 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
152 "cfg", "tchan", "rchan", "rflow";
153 bootph-all;
154};
155
156&main_mdio1_pins_default {
157 bootph-all;
158};
159
160&cpsw3g_mdio {
161 bootph-all;
162};
163
164&cpsw3g_phy0 {
165 bootph-all;
166};
167
168&main_rgmii1_pins_default {
169 bootph-all;
170};
171
172&phy_gmii_sel {
173 bootph-all;
174};
175
176&cpsw3g {
177 bootph-all;
178 ethernet-ports {
179 bootph-all;
180 };
181};
182
183&cpsw_port1 {
184 bootph-all;
Bryan Brattlofe1dd18c2022-11-03 19:13:52 -0500[diff] [blame]185};