Michal Simek | e34f1f6 | 2016-09-19 10:41:55 +0200 | [diff] [blame] | 1 | menu "FPGA support" |
| 2 | |
Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 3 | config FPGA |
| 4 | bool |
| 5 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 6 | config FPGA_ALTERA |
| 7 | bool "Enable Altera FPGA drivers" |
| 8 | select FPGA |
| 9 | help |
| 10 | Say Y here to enable the Altera FPGA driver |
| 11 | |
| 12 | This provides basic infrastructure to support Altera FPGA devices. |
| 13 | Enable Altera FPGA specific functions which includes bitstream |
| 14 | (in BIT format), fpga and device validation. |
| 15 | |
Tien Fong Chee | cde4219 | 2017-07-26 13:05:40 +0800 | [diff] [blame] | 16 | config FPGA_SOCFPGA |
| 17 | bool "Enable Gen5 and Arria10 common FPGA drivers" |
| 18 | select FPGA_ALTERA |
| 19 | help |
| 20 | Say Y here to enable the Gen5 and Arria10 common FPGA driver |
| 21 | |
| 22 | This provides common functionality for Gen5 and Arria10 devices. |
| 23 | |
Tom Rini | d1ad817 | 2022-06-12 20:02:00 -0400 | [diff] [blame] | 24 | config FPGA_STRATIX_V |
| 25 | bool "Enable Stratix V FPGA drivers" |
| 26 | depends on FPGA_ALTERA |
| 27 | help |
| 28 | Say Y here to enable the Altera Stratix V FPGA specific driver. |
| 29 | |
Alexander Dahl | cad0381 | 2022-10-07 14:19:54 +0200 | [diff] [blame] | 30 | config FPGA_ACEX1K |
| 31 | bool "Enable Altera ACEX 1K driver" |
| 32 | depends on FPGA_ALTERA |
| 33 | help |
| 34 | Say Y here to enable the Altera ACEX 1K FPGA specific driver. |
| 35 | |
Patrick Bruenn | ba81b04 | 2016-11-04 11:57:02 +0100 | [diff] [blame] | 36 | config FPGA_CYCLON2 |
| 37 | bool "Enable Altera FPGA driver for Cyclone II" |
| 38 | depends on FPGA_ALTERA |
| 39 | help |
| 40 | Say Y here to enable the Altera Cyclone II FPGA specific driver |
| 41 | |
| 42 | This provides common functionality for Altera Cyclone II devices. |
| 43 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 44 | on Altera Cyclone II device. |
| 45 | |
Chee Hong Ang | 1419245 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 46 | config FPGA_INTEL_SDM_MAILBOX |
| 47 | bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" |
Siew Chin Lim | 8a71416 | 2021-03-01 20:04:10 +0800 | [diff] [blame] | 48 | depends on TARGET_SOCFPGA_SOC64 |
Ang, Chee Hong | dcc3bb6 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 49 | select FPGA_ALTERA |
| 50 | help |
Chee Hong Ang | 1419245 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 51 | Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver |
Ang, Chee Hong | dcc3bb6 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 52 | |
Chee Hong Ang | 1419245 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 53 | This provides common functionality for Intel FPGA devices. |
| 54 | Enable FPGA driver for writing full bitstream into Intel FPGA |
| 55 | devices through SDM (Secure Device Manager) Mailbox. |
Ang, Chee Hong | dcc3bb6 | 2018-12-19 18:35:14 -0800 | [diff] [blame] | 56 | |
Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 57 | config FPGA_XILINX |
| 58 | bool "Enable Xilinx FPGA drivers" |
| 59 | select FPGA |
| 60 | help |
| 61 | Enable Xilinx FPGA specific functions which includes bitstream |
| 62 | (in BIT format), fpga and device validation. |
| 63 | |
| 64 | config FPGA_ZYNQMPPL |
| 65 | bool "Enable Xilinx FPGA driver for ZynqMP" |
| 66 | depends on FPGA_XILINX |
| 67 | help |
| 68 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 69 | on Xilinx Zynq UltraScale+ (ZynqMP) device. |
| 70 | |
Siva Durga Prasad Paladugu | b739897 | 2019-08-05 15:54:59 +0530 | [diff] [blame] | 71 | config FPGA_VERSALPL |
| 72 | bool "Enable Xilinx FPGA driver for Versal" |
| 73 | depends on FPGA_XILINX |
| 74 | help |
| 75 | Enable FPGA driver for loading bitstream in PDI format on Xilinx |
| 76 | Versal device. PDI is a new programmable device image format for |
| 77 | Versal. The bitstream will only be generated as PDI for Versal |
| 78 | platform. |
| 79 | |
Alexander Dahl | cad0381 | 2022-10-07 14:19:54 +0200 | [diff] [blame] | 80 | config FPGA_SPARTAN2 |
| 81 | bool "Enable Spartan2 FPGA driver" |
| 82 | depends on FPGA_XILINX |
| 83 | help |
| 84 | Enable Spartan2 FPGA driver. |
| 85 | |
Vipul Kumar | b8f64b9 | 2018-02-16 18:02:49 +0530 | [diff] [blame] | 86 | config FPGA_SPARTAN3 |
Michal Simek | 55af55a | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 87 | bool "Enable Spartan3 FPGA driver" |
Robert Hancock | be7f746 | 2019-06-18 09:47:13 -0600 | [diff] [blame] | 88 | depends on FPGA_XILINX |
Michal Simek | 55af55a | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 89 | help |
| 90 | Enable Spartan3 FPGA driver for loading in BIT format. |
Vipul Kumar | b8f64b9 | 2018-02-16 18:02:49 +0530 | [diff] [blame] | 91 | |
Robert Hancock | be7f746 | 2019-06-18 09:47:13 -0600 | [diff] [blame] | 92 | config FPGA_VIRTEX2 |
| 93 | bool "Enable Xilinx Virtex-II and later FPGA driver" |
| 94 | depends on FPGA_XILINX |
| 95 | help |
| 96 | Enable Virtex-II FPGA driver for loading in BIT format. This driver |
| 97 | also supports many newer Xilinx FPGA families. |
| 98 | |
Tom Rini | fe8f39a | 2022-12-04 10:03:29 -0500 | [diff] [blame] | 99 | config SYS_FPGA_CHECK_BUSY |
| 100 | bool "Perform busy check during load from FPGA" |
| 101 | depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2 |
| 102 | |
Vipul Kumar | 4a4946b | 2018-02-16 18:02:51 +0530 | [diff] [blame] | 103 | config FPGA_ZYNQPL |
Michal Simek | 55af55a | 2018-07-23 15:59:55 +0200 | [diff] [blame] | 104 | bool "Enable Xilinx FPGA for Zynq" |
| 105 | depends on ARCH_ZYNQ |
| 106 | help |
| 107 | Enable FPGA driver for loading bitstream in BIT and BIN format |
| 108 | on Xilinx Zynq devices. |
Vipul Kumar | 4a4946b | 2018-02-16 18:02:51 +0530 | [diff] [blame] | 109 | |
Alexander Dahl | 428a8c6 | 2022-07-21 15:31:21 +0200 | [diff] [blame] | 110 | config SYS_FPGA_CHECK_CTRLC |
| 111 | bool "Allow Control-C to interrupt FPGA configuration" |
| 112 | depends on FPGA |
| 113 | help |
| 114 | User can interrupt FPGA configuration by pressing CTRL+C. |
| 115 | |
Alexander Dahl | 0c46047 | 2022-07-21 15:31:22 +0200 | [diff] [blame] | 116 | config SYS_FPGA_PROG_FEEDBACK |
| 117 | bool "Progress output during FPGA configuration" |
| 118 | depends on FPGA |
| 119 | default y if FPGA_VIRTEX2 |
| 120 | help |
| 121 | Enable printing of hash marks during FPGA configuration. |
| 122 | |
Oleksandr Suvorov | fbe31bb | 2022-07-22 17:16:02 +0300 | [diff] [blame] | 123 | config FPGA_LOAD_SECURE |
| 124 | bool "Enable loading secure bitstreams" |
| 125 | depends on FPGA |
| 126 | help |
| 127 | Enables the fpga loads() functions that are used to load secure |
| 128 | (authenticated or encrypted or both) bitstreams on to FPGA. |
| 129 | |
| 130 | config SPL_FPGA_LOAD_SECURE |
| 131 | bool "Enable loading secure bitstreams for SPL" |
| 132 | depends on SPL_FPGA |
| 133 | help |
| 134 | Enables the fpga loads() functions that are used to load secure |
| 135 | (authenticated or encrypted or both) bitstreams on to FPGA. |
| 136 | |
Alexander Dahl | 6ac319d | 2022-09-30 14:04:30 +0200 | [diff] [blame] | 137 | config DM_FPGA |
| 138 | bool "Enable Driver Model for FPGA drivers" |
| 139 | depends on DM |
| 140 | select FPGA |
| 141 | help |
| 142 | Enable driver model for Field-Programmable Gate Array (FPGA) devices. |
| 143 | The devices cover a wide range of applications and are configured at |
| 144 | runtime by loading a bitstream into the FPGA device. |
| 145 | Loading a bitstream from any kind of storage is the main task of the |
| 146 | FPGA drivers. |
| 147 | For now this uclass has no methods yet. |
| 148 | |
| 149 | config SANDBOX_FPGA |
| 150 | bool "Enable sandbox FPGA driver" |
| 151 | depends on SANDBOX && DM_FPGA |
| 152 | help |
| 153 | This is a driver model based FPGA driver for sandbox. |
| 154 | Currently it is a stub only, as there are no usable uclass methods yet. |
| 155 | |
Tom Rini | 1b98e2a | 2023-01-10 11:19:37 -0500 | [diff] [blame] | 156 | config MAX_FPGA_DEVICES |
| 157 | int "Maximum number of FPGA devices" |
| 158 | depends on FPGA |
| 159 | default 5 |
| 160 | |
Michal Simek | e34f1f6 | 2016-09-19 10:41:55 +0200 | [diff] [blame] | 161 | endmenu |