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git01.mediatek.com / filogic / uboot / fd37f24d63b7ec3a9669541ada1266313f89fd31 / . / arch / arm / mach-zynqmp / Kconfig
blob: 6cf17eb94e112b991ea42a4e6d5d1fe97e131fb1 [file] [log] [blame]
Siva Durga Prasad Paladugu650fb402015-06-10 15:50:57 +0530[diff] [blame]1if ARCH_ZYNQMP
2
Tien Fong Chee6fd0a712019-01-23 14:20:03 +0800[diff] [blame]3config SPL_FS_FAT
Simon Glass6172e2e2016-09-12 23:18:38 -0600[diff] [blame]4 default y
5
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]6config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glassf6de2572016-09-12 23:18:42 -0600[diff] [blame]9config SPL_LIBDISK_SUPPORT
10 default y
11
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]12config SPL_LIBGENERIC_SUPPORT
13 default y
14
Simon Glassbd58f1d2016-09-12 23:18:44 -0600[diff] [blame]15config SPL_MMC_SUPPORT
Alexandru Gagniucd5a75992017-04-04 10:02:58 -0700[diff] [blame]16 default y if MMC_SDHCI_ZYNQ
Simon Glassbd58f1d2016-09-12 23:18:44 -0600[diff] [blame]17
Simon Glasse076d6f2016-09-12 23:18:56 -0600[diff] [blame]18config SPL_SERIAL_SUPPORT
19 default y
20
Simon Glass219d6122016-09-12 23:18:57 -0600[diff] [blame]21config SPL_SPI_FLASH_SUPPORT
22 default y if ZYNQ_QSPI
23
Simon Glassb24fdca2016-09-12 23:18:58 -0600[diff] [blame]24config SPL_SPI_SUPPORT
25 default y if ZYNQ_QSPI
26
Michal Simek04b7e622015-01-15 10:01:51 +0100[diff] [blame]27config SYS_BOARD
28 default "zynqmp"
29
30config SYS_VENDOR
Mike Looijmans61d245c2017-01-03 09:47:52 +0100[diff] [blame]31 string "Vendor name"
Michal Simek04b7e622015-01-15 10:01:51 +0100[diff] [blame]32 default "xilinx"
33
34config SYS_SOC
35 default "zynqmp"
36
37config SYS_CONFIG_NAME
Michal Simek7b5413e2016-03-18 18:21:36 +0100[diff] [blame]38 string "Board configuration name"
39 default "xilinx_zynqmp"
40 help
41 This option contains information about board configuration name.
42 Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
43 will be used for board configuration.
Michal Simek04b7e622015-01-15 10:01:51 +0100[diff] [blame]44
Siva Durga Prasad Paladugu4628c502017-07-13 19:01:11 +0530[diff] [blame]45config SYS_MEM_RSVD_FOR_MMU
46 bool "Reserve memory for MMU Table"
47 help
48 If defined this option is used to setup different space for
49 MMU table than the one which will be allocated during
50 relocation.
51
Mike Looijmans96e706f2016-09-20 11:37:24 +0200[diff] [blame]52config BOOT_INIT_FILE
53 string "boot.bin init register filename"
Michal Simek5d359092016-12-16 13:00:26 +0100[diff] [blame]54 depends on SPL
Mike Looijmans96e706f2016-09-20 11:37:24 +0200[diff] [blame]55 default ""
56 help
57 Add register writes to boot.bin format (max 256 pairs).
58 Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
59
Michal Simekdde5a882016-10-21 12:58:17 +0200[diff] [blame]60config PMUFW_INIT_FILE
61 string "PMU firmware"
62 depends on SPL
63 default ""
64 help
65 Include external PMUFW (Platform Management Unit FirmWare) to
66 a Xilinx bootable image (boot.bin).
67
Luca Ceresoli23e65002019-05-21 18:06:43 +0200[diff] [blame]68config ZYNQMP_SPL_PM_CFG_OBJ_FILE
69 string "PMU firmware configuration object to load at runtime by SPL"
70 depends on SPL
71 help
72 Path to a binary PMU firmware configuration object to be linked
73 into U-Boot SPL and loaded at runtime into the PMU firmware.
74
75 The ZynqMP Power Management Unit (PMU) needs a configuration
76 object for most SoC peripherals to work. To have it loaded by
77 U-Boot SPL set here the file name (absolute path or relative to
78 the top source tree) of your configuration, which must be a
79 binary blob. It will be linked in the SPL binary and loaded
80 into the PMU firmware by U-Boot SPL during board
81 initialization.
82
83 Leave this option empty if your PMU firmware has a hard-coded
84 configuration object or you are loading it by any other means.
85
Siva Durga Prasad Paladuguba1f68e2015-08-04 13:03:26 +0530[diff] [blame]86config ZYNQMP_USB
87 bool "Configure ZynqMP USB"
88
Siva Durga Prasad Paladugucafb6312018-01-12 15:35:46 +0530[diff] [blame]89config ZYNQMP_NO_DDR
90 bool "Disable DDR MMU mapping"
91 help
92 This option configures MMU with no DDR to avoid speculative
93 access to DDR memory where DDR is not present.
94
Simon Glasscb3e4892016-07-05 17:10:13 -0600[diff] [blame]95config SYS_MALLOC_F_LEN
96 default 0x600
97
Siva Durga Prasad Paladugu9ed4e812017-07-13 19:01:10 +0530[diff] [blame]98config DEFINE_TCM_OCM_MMAP
99 bool "Define TCM and OCM memory in MMU Table"
Siva Durga Prasad Paladuguc3dfac92017-08-01 16:24:50 +0530[diff] [blame]100 default y if MP
Siva Durga Prasad Paladugu9ed4e812017-07-13 19:01:10 +0530[diff] [blame]101 help
102 This option if enabled defines the TCM and OCM memory and its
103 memory attributes in MMU table entry.
104
Michal Simekd8218792017-07-12 13:21:27 +0200[diff] [blame]105config ZYNQMP_PSU_INIT_ENABLED
106 bool "Include psu_init"
107 help
108 Include psu_init to full u-boot. SPL include psu_init by default.
109
Michal Simek94ddcaa2016-08-30 16:17:27 +0200[diff] [blame]110config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
111 bool "Overwrite SPL bootmode"
112 depends on SPL
113 help
114 Overwrite bootmode selected via boot mode pins to tell SPL what should
115 be the next boot device.
116
Vipul Kumar62548002018-02-28 15:53:28 +0530[diff] [blame]117config ZYNQ_SDHCI_MAX_FREQ
118 default 200000000
119
Michal Simeked47b9e2019-02-13 13:46:41 +0100[diff] [blame]120config SPL_ZYNQMP_TWO_SDHCI
121 bool "Enable booting from both SDHCIs"
122 depends on SPL
123 help
124 This option reflects that board has two SDHCI controllers which
125 platform can use as boot device. This option ensures that SPL will
126 setup BOOT_DEVICE_MMC2 for SDHCI1 controller and BOOT_DEVICE_MMC1 for
127 SDHCI0 controller. Platforms which have only one SDHCI controller
128 shouldn't enable this option because it for software SDHCI0 or SDHCI1
129 are both covered by BOOT_DEVICE_MMC1.
130
Michal Simek94ddcaa2016-08-30 16:17:27 +0200[diff] [blame]131config SPL_ZYNQMP_ALT_BOOTMODE
132 hex
133 default 0x0 if JTAG_MODE
134 default 0x1 if QSPI_MODE_24BIT
135 default 0x2 if QSPI_MODE_32BIT
136 default 0x3 if SD_MODE
137 default 0x4 if NAND_MODE
138 default 0x5 if SD_MODE1
139 default 0x6 if EMMC_MODE
140 default 0x7 if USB_MODE
Michal Simek2740d372016-10-26 09:24:32 +0200[diff] [blame]141 default 0xa if SW_USBHOST_MODE
142 default 0xb if SW_SATA_MODE
Michal Simeke1c4d392017-02-15 09:41:53 +0100[diff] [blame]143 default 0xe if SD1_LSHFT_MODE
Michal Simek94ddcaa2016-08-30 16:17:27 +0200[diff] [blame]144
145choice
146 prompt "Boot mode"
Michal Simek8ffddc32016-08-30 16:17:27 +0200[diff] [blame]147 depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
Ulf Magnusson3e3b16a2018-01-30 14:02:01 +0100[diff] [blame]148 default JTAG_MODE
Michal Simek94ddcaa2016-08-30 16:17:27 +0200[diff] [blame]149
150config JTAG_MODE
151 bool "JTAG_MODE"
152
153config QSPI_MODE_24BIT
154 bool "QSPI_MODE_24BIT"
155
156config QSPI_MODE_32BIT
157 bool "QSPI_MODE_32BIT"
158
159config SD_MODE
160 bool "SD_MODE"
161
162config SD_MODE1
163 bool "SD_MODE1"
164
165config NAND_MODE
166 bool "NAND_MODE"
167
168config EMMC_MODE
169 bool "EMMC_MODE"
170
171config USB_MODE
172 bool "USB"
173
Michal Simek2740d372016-10-26 09:24:32 +0200[diff] [blame]174config SW_USBHOST_MODE
175 bool "SW USBHOST_MODE"
176
177config SW_SATA_MODE
178 bool "SW SATA_MODE"
179
Michal Simeke1c4d392017-02-15 09:41:53 +0100[diff] [blame]180config SD1_LSHFT_MODE
181 bool "SD1_LSHFT_MODE"
182
Michal Simek94ddcaa2016-08-30 16:17:27 +0200[diff] [blame]183endchoice
Simon Glasscb3e4892016-07-05 17:10:13 -0600[diff] [blame]184
Michal Simek04b7e622015-01-15 10:01:51 +0100[diff] [blame]185endif