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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +01002/*
3 * Copyright (C) 2016, Imagination Technologies Ltd.
4 *
5 * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
6 *
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +01007 * Imagination Technologies Ltd. MIPSfpga
8 */
9
10#ifndef __XILFPGA_CONFIG_H
11#define __XILFPGA_CONFIG_H
12
13/* BootROM + MIG is pretty smart. DDR and Cache initialized */
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010014
15/*--------------------------------------------
16 * CPU configuration
17 */
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010018
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010019/*----------------------------------------------------------------------
20 * Memory Layout
21 */
22
23/* SDRAM Configuration (for final code, data, stack, heap) */
Tom Rinibb4dd962022-11-16 13:10:37 -050024#define CFG_SYS_SDRAM_BASE 0x80000000
25#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010026
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010027/*----------------------------------------------------------------------
28 * Commands
29 */
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010030
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010031/*------------------------------------------------------------
32 * Console Configuration
33 */
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010034
35/* -------------------------------------------------
36 * Environment
37 */
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010038
39/* ---------------------------------------------------------------------
40 * Board boot configuration
41 */
Zubair Lutfullah Kakakhel1d153b32016-07-29 15:11:20 +010042
43#endif /* __XILFPGA_CONFIG_H */