Lukasz Majewski | 137419a | 2019-06-19 17:31:06 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2019 DENX Software Engineering |
| 4 | * Lukasz Majewski, DENX Software Engineering, lukma@denx.de |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <linux/io.h> |
| 9 | #include <linux/err.h> |
| 10 | #include <dm.h> |
| 11 | #include <dm/pinctrl.h> |
| 12 | #include <dm/read.h> |
| 13 | #include "pinctrl-mxs.h" |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | struct mxs_pinctrl_priv { |
| 18 | void __iomem *base; |
| 19 | const struct mxs_regs *regs; |
| 20 | }; |
| 21 | |
| 22 | static unsigned long mxs_dt_node_to_map(struct udevice *conf) |
| 23 | { |
| 24 | unsigned long config = 0; |
| 25 | int ret; |
| 26 | u32 val; |
| 27 | |
| 28 | ret = dev_read_u32(conf, "fsl,drive-strength", &val); |
| 29 | if (!ret) |
| 30 | config = val | MA_PRESENT; |
| 31 | |
| 32 | ret = dev_read_u32(conf, "fsl,voltage", &val); |
| 33 | if (!ret) |
| 34 | config |= val << VOL_SHIFT | VOL_PRESENT; |
| 35 | |
| 36 | ret = dev_read_u32(conf, "fsl,pull-up", &val); |
| 37 | if (!ret) |
| 38 | config |= val << PULL_SHIFT | PULL_PRESENT; |
| 39 | |
| 40 | return config; |
| 41 | } |
| 42 | |
| 43 | static int mxs_pinctrl_set_mux(struct udevice *dev, u32 val, int bank, int pin) |
| 44 | { |
| 45 | struct mxs_pinctrl_priv *iomux = dev_get_priv(dev); |
| 46 | int muxsel = MUXID_TO_MUXSEL(val), shift; |
| 47 | void __iomem *reg; |
| 48 | |
| 49 | reg = iomux->base + iomux->regs->muxsel; |
| 50 | reg += bank * 0x20 + pin / 16 * 0x10; |
| 51 | shift = pin % 16 * 2; |
| 52 | |
| 53 | mxs_pinctrl_rmwl(muxsel, 0x3, shift, reg); |
| 54 | debug(" mux %d,", muxsel); |
| 55 | |
| 56 | return 0; |
| 57 | } |
| 58 | |
| 59 | static int mxs_pinctrl_set_state(struct udevice *dev, struct udevice *conf) |
| 60 | { |
| 61 | struct mxs_pinctrl_priv *iomux = dev_get_priv(dev); |
| 62 | u32 *pin_data, val, ma, vol, pull; |
| 63 | int npins, size, i, ret; |
| 64 | unsigned long config; |
| 65 | |
| 66 | debug("\n%s: set state: %s\n", __func__, conf->name); |
| 67 | |
| 68 | size = dev_read_size(conf, "fsl,pinmux-ids"); |
| 69 | if (size < 0) |
| 70 | return size; |
| 71 | |
| 72 | if (!size || size % sizeof(int)) { |
| 73 | dev_err(dev, "Invalid fsl,pinmux-ids property in %s\n", |
| 74 | conf->name); |
| 75 | return -EINVAL; |
| 76 | } |
| 77 | |
| 78 | npins = size / sizeof(int); |
| 79 | |
| 80 | pin_data = devm_kzalloc(dev, size, 0); |
| 81 | if (!pin_data) |
| 82 | return -ENOMEM; |
| 83 | |
| 84 | ret = dev_read_u32_array(conf, "fsl,pinmux-ids", pin_data, npins); |
| 85 | if (ret) { |
| 86 | dev_err(dev, "Error reading pin data.\n"); |
| 87 | devm_kfree(dev, pin_data); |
| 88 | return -EINVAL; |
| 89 | } |
| 90 | |
| 91 | config = mxs_dt_node_to_map(conf); |
| 92 | |
| 93 | ma = CONFIG_TO_MA(config); |
| 94 | vol = CONFIG_TO_VOL(config); |
| 95 | pull = CONFIG_TO_PULL(config); |
| 96 | |
| 97 | for (i = 0; i < npins; i++) { |
| 98 | int pinid, bank, pin, shift; |
| 99 | void __iomem *reg; |
| 100 | |
| 101 | val = pin_data[i]; |
| 102 | |
| 103 | pinid = MUXID_TO_PINID(val); |
| 104 | bank = PINID_TO_BANK(pinid); |
| 105 | pin = PINID_TO_PIN(pinid); |
| 106 | |
| 107 | debug("(val: 0x%x) pin %d,", val, pinid); |
| 108 | /* Setup pinmux */ |
| 109 | mxs_pinctrl_set_mux(dev, val, bank, pin); |
| 110 | |
| 111 | debug(" ma: %d, vol: %d, pull: %d\n", ma, vol, pull); |
| 112 | |
| 113 | /* drive */ |
| 114 | reg = iomux->base + iomux->regs->drive; |
| 115 | reg += bank * 0x40 + pin / 8 * 0x10; |
| 116 | |
| 117 | /* mA */ |
| 118 | if (config & MA_PRESENT) { |
| 119 | shift = pin % 8 * 4; |
| 120 | mxs_pinctrl_rmwl(ma, 0x3, shift, reg); |
| 121 | } |
| 122 | |
| 123 | /* vol */ |
| 124 | if (config & VOL_PRESENT) { |
| 125 | shift = pin % 8 * 4 + 2; |
| 126 | if (vol) |
| 127 | writel(1 << shift, reg + SET); |
| 128 | else |
| 129 | writel(1 << shift, reg + CLR); |
| 130 | } |
| 131 | |
| 132 | /* pull */ |
| 133 | if (config & PULL_PRESENT) { |
| 134 | reg = iomux->base + iomux->regs->pull; |
| 135 | reg += bank * 0x10; |
| 136 | shift = pin; |
| 137 | if (pull) |
| 138 | writel(1 << shift, reg + SET); |
| 139 | else |
| 140 | writel(1 << shift, reg + CLR); |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | devm_kfree(dev, pin_data); |
| 145 | return 0; |
| 146 | } |
| 147 | |
| 148 | static struct pinctrl_ops mxs_pinctrl_ops = { |
| 149 | .set_state = mxs_pinctrl_set_state, |
| 150 | }; |
| 151 | |
| 152 | static int mxs_pinctrl_probe(struct udevice *dev) |
| 153 | { |
| 154 | struct mxs_pinctrl_priv *iomux = dev_get_priv(dev); |
| 155 | |
| 156 | iomux->base = dev_read_addr_ptr(dev); |
| 157 | iomux->regs = (struct mxs_regs *)dev_get_driver_data(dev); |
| 158 | |
| 159 | return 0; |
| 160 | } |
| 161 | |
| 162 | static const struct mxs_regs imx23_regs = { |
| 163 | .muxsel = 0x100, |
| 164 | .drive = 0x200, |
| 165 | .pull = 0x400, |
| 166 | }; |
| 167 | |
| 168 | static const struct mxs_regs imx28_regs = { |
| 169 | .muxsel = 0x100, |
| 170 | .drive = 0x300, |
| 171 | .pull = 0x600, |
| 172 | }; |
| 173 | |
| 174 | static const struct udevice_id mxs_pinctrl_match[] = { |
| 175 | { .compatible = "fsl,imx23-pinctrl", .data = (ulong)&imx23_regs }, |
| 176 | { .compatible = "fsl,imx28-pinctrl", .data = (ulong)&imx28_regs }, |
| 177 | { /* sentinel */ } |
| 178 | }; |
| 179 | |
| 180 | U_BOOT_DRIVER(mxs_pinctrl) = { |
| 181 | .name = "mxs-pinctrl", |
| 182 | .id = UCLASS_PINCTRL, |
| 183 | .of_match = of_match_ptr(mxs_pinctrl_match), |
| 184 | .probe = mxs_pinctrl_probe, |
| 185 | #if !CONFIG_IS_ENABLED(OF_PLATDATA) |
| 186 | .bind = dm_scan_fdt_dev, |
| 187 | #endif |
| 188 | .priv_auto_alloc_size = sizeof(struct mxs_pinctrl_priv), |
| 189 | .ops = &mxs_pinctrl_ops, |
| 190 | }; |