blob: 85f1f6344adf5782b60f50fac543d5249f322562 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Xie Xiaoboac193882013-06-24 15:01:30 +08002/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Xie Xiaoboac193882013-06-24 15:01:30 +08004 */
5
6#include <common.h>
Simon Glassf5c208d2019-11-14 12:57:20 -07007#include <vsprintf.h>
Xie Xiaoboac193882013-06-24 15:01:30 +08008#include <asm/mmu.h>
9#include <asm/immap_85xx.h>
10#include <asm/processor.h>
York Sunf0626592013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
Xie Xiaoboac193882013-06-24 15:01:30 +080013#include <asm/io.h>
14#include <asm/fsl_law.h>
15
16/* Fixed sdram init -- doesn't use serial presence detect. */
17phys_size_t fixed_sdram(void)
18{
19 sys_info_t sysinfo;
20 char buf[32];
21 size_t ddr_size;
22 fsl_ddr_cfg_regs_t ddr_cfg_regs = {
23 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
24 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
25 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
26#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
27 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
28 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
29 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
30#endif
31 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
32 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
33 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
34 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
35 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
36 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
37 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
38 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
39 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
40 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
41 .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
42 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
43 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
44 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
45 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
46 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
47 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
48 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
49 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
50 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
51 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
52 };
53
54 get_sys_info(&sysinfo);
55 printf("Configuring DDR for %s MT/s data rate\n",
Prabhakar Kushwahad1698082013-08-16 14:52:26 +053056 strmhz(buf, sysinfo.freq_ddrbus));
Xie Xiaoboac193882013-06-24 15:01:30 +080057
58 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
59
York Sun5e155552013-06-25 11:37:48 -070060 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
Xie Xiaoboac193882013-06-24 15:01:30 +080061
62 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
63 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
64 printf("ERROR setting Local Access Windows for DDR\n");
65 return 0;
66 };
67
68 return ddr_size;
69}