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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jason Liudec11122011-11-25 00:18:02 +00002/*
3 * (C) Copyright 2009
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
Jason Liudec11122011-11-25 00:18:02 +00005 */
6
7#ifndef __ASM_ARCH_CLOCK_H
8#define __ASM_ARCH_CLOCK_H
9
Simon Glass1e268642020-05-10 11:39:55 -060010#include <linux/types.h>
Benoît Thébaudeauafac1652012-09-27 10:19:58 +000011
12#ifdef CONFIG_SYS_MX6_HCLK
13#define MXC_HCLK CONFIG_SYS_MX6_HCLK
14#else
15#define MXC_HCLK 24000000
16#endif
17
18#ifdef CONFIG_SYS_MX6_CLK32
19#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
20#else
21#define MXC_CLK32 32768
22#endif
23
Simon Glassed38aef2020-05-10 11:40:03 -060024struct cmd_tbl;
Simon Glass1e268642020-05-10 11:39:55 -060025
Jason Liudec11122011-11-25 00:18:02 +000026enum mxc_clock {
27 MXC_ARM_CLK = 0,
28 MXC_PER_CLK,
29 MXC_AHB_CLK,
30 MXC_IPG_CLK,
31 MXC_IPG_PERCLK,
32 MXC_UART_CLK,
33 MXC_CSPI_CLK,
34 MXC_AXI_CLK,
35 MXC_EMI_SLOW_CLK,
36 MXC_DDR_CLK,
37 MXC_ESDHC_CLK,
38 MXC_ESDHC2_CLK,
39 MXC_ESDHC3_CLK,
40 MXC_ESDHC4_CLK,
41 MXC_SATA_CLK,
42 MXC_NFC_CLK,
Matthias Weisser99ba3422012-09-24 02:46:53 +000043 MXC_I2C_CLK,
Jason Liudec11122011-11-25 00:18:02 +000044};
45
Akshay Bhat4e364e62016-04-12 18:13:56 -040046enum ldb_di_clock {
47 MXC_PLL5_CLK = 0,
48 MXC_PLL2_PFD0_CLK,
49 MXC_PLL2_PFD2_CLK,
50 MXC_MMDC_CH1_CLK,
51 MXC_PLL3_SW_CLK,
52};
53
Fabio Estevamb2903ae2014-01-03 15:55:57 -020054enum enet_freq {
Stefan Roesed7e07312014-11-27 13:46:43 +010055 ENET_25MHZ,
56 ENET_50MHZ,
57 ENET_100MHZ,
58 ENET_125MHZ,
Fabio Estevamb2903ae2014-01-03 15:55:57 -020059};
60
Jason Liudec11122011-11-25 00:18:02 +000061u32 imx_get_uartclk(void);
62u32 imx_get_fecclk(void);
63unsigned int mxc_get_clock(enum mxc_clock clk);
Nikita Kiryanov98b76b42014-08-20 15:08:49 +030064void setup_gpmi_io_clk(u32 cfg);
Nitin Gargb1ce7012014-09-16 13:33:25 -050065void hab_caam_clock_enable(unsigned char enable);
Benoît Thébaudeau20db6312013-04-23 10:17:44 +000066void enable_ocotp_clk(unsigned char enable);
Wolfgang Grandegger1859b702012-02-08 22:33:25 +000067void enable_usboh3_clk(unsigned char enable);
Nikita Kiryanov98b76b42014-08-20 15:08:49 +030068void enable_uart_clk(unsigned char enable);
Nikita Kiryanov98b76b42014-08-20 15:08:49 +030069int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
Eric Nelsonfdba0762012-03-27 09:52:21 +000070int enable_sata_clock(void);
Nikita Kiryanov63659b72014-11-21 12:47:22 +020071void disable_sata_clock(void);
Marek Vasut563dfb22013-12-14 06:27:26 +010072int enable_pcie_clock(void);
Troy Kiskyd4fdc992012-07-19 08:18:25 +000073int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
Heiko Schocher472a68f2014-07-18 06:07:20 +020074int enable_spi_clk(unsigned char enable, unsigned spi_num);
Pardeep Kumar Singlac1fa1302013-07-25 12:12:13 -050075void enable_ipu_clock(void);
Fabio Estevam1b6c50e2019-07-12 09:32:23 -030076void disable_ipu_clock(void);
Peng Fan967a83b2015-08-12 17:46:50 +080077int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
Nikita Kiryanov98b76b42014-08-20 15:08:49 +030078void enable_enet_clk(unsigned char enable);
Peng Fan4bbd7422016-12-11 19:24:28 +080079int enable_lcdif_clock(u32 base_addr, bool enable);
Peng Fan828e4682014-12-31 11:01:38 +080080void enable_qspi_clk(int qspi_num);
Nitin Garg59f3be32014-11-20 21:14:12 +080081void enable_thermal_clk(void);
Peng Fan53ebda82015-10-29 15:54:47 +080082void mxs_set_lcdclk(u32 base_addr, u32 freq);
Akshay Bhat4e364e62016-04-12 18:13:56 -040083void select_ldb_di_clock_source(enum ldb_di_clock clk);
Lukasz Majewski529498e2016-11-28 07:18:14 +010084void enable_eim_clk(unsigned char enable);
Simon Glassed38aef2020-05-10 11:40:03 -060085int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
Simon Glass1e268642020-05-10 11:39:55 -060086 char *const argv[]);
Jason Liudec11122011-11-25 00:18:02 +000087#endif /* __ASM_ARCH_CLOCK_H */