Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / fc85ec5ec7f63cfa4a85629a9b8e055e1bfee8e2 / . / arch / arm / cpu / armv7 / ls102xa / fsl_epu.c
blob: e31a4fb6c31bb439790c8e2159a2bd4de85542bb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
chenhui zhao0c789872014-10-22 18:20:22 +0800[diff] [blame]2/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
chenhui zhao0c789872014-10-22 18:20:22 +0800[diff] [blame]4 */
5
6#include <common.h>
7#include <asm/io.h>
8
9#include "fsl_epu.h"
10
Hongbo Zhang4ea6d6f2016-08-19 17:20:32 +0800[diff] [blame]11struct fsm_reg_vals epu_default_val[] = {
12 /* EPGCR (Event Processor Global Control Register) */
13 {EPGCR, 0},
14 /* EPECR (Event Processor Event Control Registers) */
15 {EPECR0 + EPECR_STRIDE * 0, 0},
16 {EPECR0 + EPECR_STRIDE * 1, 0},
17 {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
18 {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
19 {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
20 {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
21 {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
22 {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
23 {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
24 {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
25 {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
26 {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
27 {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
28 {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
29 {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
30 {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
31 /*
32 * EPEVTCR (Event Processor EVT Pin Control Registers)
33 * SCU8 triger EVT2, and SCU11 triger EVT9
34 */
35 {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
36 {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
37 {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
38 {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
39 {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
40 {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
41 {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
42 {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
43 {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
44 {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
45 /* EPCMPR (Event Processor Counter Compare Registers) */
46 {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
47 {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
48 {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
49 {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
50 {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
51 {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
52 {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
53 {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
54 {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
55 {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
56 {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
57 {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
58 {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
59 {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
60 {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
61 {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
62 /* EPCCR (Event Processor Counter Control Registers) */
63 {EPCCR0 + EPCCR_STRIDE * 0, 0},
64 {EPCCR0 + EPCCR_STRIDE * 1, 0},
65 {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
66 {EPCCR0 + EPCCR_STRIDE * 3, 0},
67 {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
68 {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
69 {EPCCR0 + EPCCR_STRIDE * 6, 0},
70 {EPCCR0 + EPCCR_STRIDE * 7, 0},
71 {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
72 {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
73 {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
74 {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
75 {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
76 {EPCCR0 + EPCCR_STRIDE * 13, 0},
77 {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
78 {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
79 /* EPSMCR (Event Processor SCU Mux Control Registers) */
80 {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
81 {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
82 {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
83 {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
84 {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
85 {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
86 {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
87 {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
88 {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
89 {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
90 {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
91 {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
92 {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
93 {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
94 {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
95 {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
96 /* EPACR (Event Processor Action Control Registers) */
97 {EPACR0 + EPACR_STRIDE * 0, 0},
98 {EPACR0 + EPACR_STRIDE * 1, 0},
99 {EPACR0 + EPACR_STRIDE * 2, 0},
100 {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
101 {EPACR0 + EPACR_STRIDE * 4, 0},
102 {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
103 {EPACR0 + EPACR_STRIDE * 6, 0},
104 {EPACR0 + EPACR_STRIDE * 7, 0},
105 {EPACR0 + EPACR_STRIDE * 8, 0},
106 {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
107 {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
108 {EPACR0 + EPACR_STRIDE * 11, 0},
109 {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
110 {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
111 {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
112 {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
113 /* EPIMCR (Event Processor Input Mux Control Registers) */
114 {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
115 {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
116 {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
117 {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
118 {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
119 {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
120 {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
121 {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
122 {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
123 {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
124 {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
125 {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
126 {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
127 {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
128 {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
129 {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
130 {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
131 {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
132 {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
133 {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
134 {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
135 {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
136 {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
137 {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
138 {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
139 {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
140 {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
141 {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
142 {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
143 {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
144 {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
145 {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
146 /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
147 {EPXTRIGCR, 0x0000FFDF},
148 /* end */
149 {FSM_END_FLAG, 0},
150};
151
152/**
153 * fsl_epu_setup - Setup EPU registers to default values
154 */
155void fsl_epu_setup(void *epu_base)
156{
157 struct fsm_reg_vals *data = epu_default_val;
158
159 if (!epu_base || !data)
160 return;
161
162 while (data->offset != FSM_END_FLAG) {
163 out_be32(epu_base + data->offset, data->value);
164 data++;
165 }
166}
167
chenhui zhao0c789872014-10-22 18:20:22 +0800[diff] [blame]168/**
169 * fsl_epu_clean - Clear EPU registers
170 */
171void fsl_epu_clean(void *epu_base)
172{
173 u32 offset;
174
175 /* follow the exact sequence to clear the registers */
176 /* Clear EPACRn */
177 for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
178 out_be32(epu_base + offset, 0);
179
180 /* Clear EPEVTCRn */
181 for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
182 out_be32(epu_base + offset, 0);
183
184 /* Clear EPGCR */
185 out_be32(epu_base + EPGCR, 0);
186
187 /* Clear EPSMCRn */
188 for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
189 out_be32(epu_base + offset, 0);
190
191 /* Clear EPCCRn */
192 for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
193 out_be32(epu_base + offset, 0);
194
195 /* Clear EPCMPRn */
196 for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
197 out_be32(epu_base + offset, 0);
198
199 /* Clear EPCTRn */
200 for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
201 out_be32(epu_base + offset, 0);
202
203 /* Clear EPIMCRn */
204 for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
205 out_be32(epu_base + offset, 0);
206
207 /* Clear EPXTRIGCRn */
208 out_be32(epu_base + EPXTRIGCR, 0);
209
210 /* Clear EPECRn */
211 for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
212 out_be32(epu_base + offset, 0);
213}