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git01.mediatek.com / filogic / uboot / fc805c2d88fc0bbe52837ae7c0f258a963e5fe47 / . / arch / arm / mach-tegra / tegra20 / Kconfig
blob: 57d11024bfc23e3d2369e67ed9072c0115d31e57 [file] [log] [blame]
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]1if TEGRA20
2
Tom Rini117af432022-11-19 18:45:36 -0500[diff] [blame]3config TEGRA_LP0
4 bool
5 select TEGRA_CLOCK_SCALING
Svyatoslav Ryhel7d5a2f42023-02-14 19:35:35 +0200[diff] [blame]6 select TEGRA_CRYPTO
Tom Rini117af432022-11-19 18:45:36 -0500[diff] [blame]7
8config TEGRA_PMU
9 bool
10
11config TEGRA_CLOCK_SCALING
12 bool
13
Tom Rini4b3e7c02022-12-02 16:42:45 -0500[diff] [blame]14config TEGRA_UARTA_GPU
15 bool
16
17config TEGRA_UARTA_SDIO1
18 bool
19
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]20choice
21 prompt "Tegra20 board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]22 optional
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]23
24config TARGET_HARMONY
25 bool "NVIDIA Tegra20 Harmony evaluation board"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]26 select BOARD_LATE_INIT
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]27
28config TARGET_MEDCOM_WIDE
29 bool "Avionic Design Medcom-Wide board"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]30 select BOARD_LATE_INIT
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]31
32config TARGET_PAZ00
33 bool "Paz00 board"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]34 select BOARD_LATE_INIT
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]35
36config TARGET_PLUTUX
37 bool "Avionic Design Plutux board"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]38 select BOARD_LATE_INIT
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]39
40config TARGET_SEABOARD
41 bool "NVIDIA Seaboard"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]42 select BOARD_LATE_INIT
Tom Rini117af432022-11-19 18:45:36 -0500[diff] [blame]43 select TEGRA_LP0
44 select TEGRA_PMU
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]45
46config TARGET_TEC
47 bool "Avionic Design Tamonten Evaluation Carrier"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]48 select BOARD_LATE_INIT
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]49
50config TARGET_TRIMSLICE
51 bool "Compulab TrimSlice board"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]52 select BOARD_LATE_INIT
Tom Rini4b3e7c02022-12-02 16:42:45 -0500[diff] [blame]53 select TEGRA_UARTA_GPU
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]54
55config TARGET_VENTANA
56 bool "NVIDIA Tegra20 Ventana evaluation board"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]57 select BOARD_LATE_INIT
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]58
Marcel Ziswilercad18b82015-03-26 01:31:54 +0100[diff] [blame]59config TARGET_COLIBRI_T20
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]60 bool "Toradex Colibri T20 board"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]61 select BOARD_LATE_INIT
Tom Rini4b3e7c02022-12-02 16:42:45 -0500[diff] [blame]62 select TEGRA_UARTA_SDIO1
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]63
64endchoice
65
66config SYS_SOC
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]67 default "tegra20"
68
69source "board/nvidia/harmony/Kconfig"
70source "board/avionic-design/medcom-wide/Kconfig"
71source "board/compal/paz00/Kconfig"
72source "board/avionic-design/plutux/Kconfig"
73source "board/nvidia/seaboard/Kconfig"
74source "board/avionic-design/tec/Kconfig"
75source "board/compulab/trimslice/Kconfig"
76source "board/nvidia/ventana/Kconfig"
Marcel Ziswilercad18b82015-03-26 01:31:54 +0100[diff] [blame]77source "board/toradex/colibri_t20/Kconfig"
Masahiro Yamada73a5b1a2014-08-31 07:10:56 +0900[diff] [blame]78
79endif