Heiko Stuebner | fc36785 | 2019-07-16 22:18:21 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2017 Rockchip Electronics Co., Ltd |
| 4 | */ |
| 5 | #include <common.h> |
| 6 | #include <clk.h> |
| 7 | #include <dm.h> |
| 8 | #include <asm/armv8/mmu.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch-rockchip/grf_px30.h> |
| 11 | #include <asm/arch-rockchip/hardware.h> |
| 12 | #include <asm/arch-rockchip/uart.h> |
| 13 | #include <asm/arch-rockchip/clock.h> |
| 14 | #include <asm/arch-rockchip/cru_px30.h> |
| 15 | #include <dt-bindings/clock/px30-cru.h> |
| 16 | |
| 17 | static struct mm_region px30_mem_map[] = { |
| 18 | { |
| 19 | .virt = 0x0UL, |
| 20 | .phys = 0x0UL, |
| 21 | .size = 0xff000000UL, |
| 22 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 23 | PTE_BLOCK_INNER_SHARE |
| 24 | }, { |
| 25 | .virt = 0xff000000UL, |
| 26 | .phys = 0xff000000UL, |
| 27 | .size = 0x01000000UL, |
| 28 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 29 | PTE_BLOCK_NON_SHARE | |
| 30 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 31 | }, { |
| 32 | /* List terminator */ |
| 33 | 0, |
| 34 | } |
| 35 | }; |
| 36 | |
| 37 | struct mm_region *mem_map = px30_mem_map; |
| 38 | |
| 39 | #define PMU_PWRDN_CON 0xff000018 |
| 40 | #define GRF_BASE 0xff140000 |
| 41 | #define CRU_BASE 0xff2b0000 |
| 42 | #define VIDEO_PHY_BASE 0xff2e0000 |
| 43 | #define SERVICE_CORE_ADDR 0xff508000 |
| 44 | #define DDR_FW_BASE 0xff534000 |
| 45 | |
| 46 | #define FW_DDR_CON 0x40 |
| 47 | |
| 48 | #define QOS_PRIORITY 0x08 |
| 49 | |
| 50 | #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3)) |
| 51 | |
| 52 | /* GRF_GPIO1CL_IOMUX */ |
| 53 | enum { |
| 54 | GPIO1C1_SHIFT = 4, |
| 55 | GPIO1C1_MASK = 0xf << GPIO1C1_SHIFT, |
| 56 | GPIO1C1_GPIO = 0, |
| 57 | GPIO1C1_UART1_TX, |
| 58 | |
| 59 | GPIO1C0_SHIFT = 0, |
| 60 | GPIO1C0_MASK = 0xf << GPIO1C0_SHIFT, |
| 61 | GPIO1C0_GPIO = 0, |
| 62 | GPIO1C0_UART1_RX, |
| 63 | }; |
| 64 | |
| 65 | /* GRF_GPIO1DL_IOMUX */ |
| 66 | enum { |
| 67 | GPIO1D3_SHIFT = 12, |
| 68 | GPIO1D3_MASK = 0xf << GPIO1D3_SHIFT, |
| 69 | GPIO1D3_GPIO = 0, |
| 70 | GPIO1D3_SDMMC_D1, |
| 71 | GPIO1D3_UART2_RXM0, |
| 72 | |
| 73 | GPIO1D2_SHIFT = 8, |
| 74 | GPIO1D2_MASK = 0xf << GPIO1D2_SHIFT, |
| 75 | GPIO1D2_GPIO = 0, |
| 76 | GPIO1D2_SDMMC_D0, |
| 77 | GPIO1D2_UART2_TXM0, |
| 78 | }; |
| 79 | |
| 80 | /* GRF_GPIO1DH_IOMUX */ |
| 81 | enum { |
| 82 | GPIO1D7_SHIFT = 12, |
| 83 | GPIO1D7_MASK = 0xf << GPIO1D7_SHIFT, |
| 84 | GPIO1D7_GPIO = 0, |
| 85 | GPIO1D7_SDMMC_CMD, |
| 86 | |
| 87 | GPIO1D6_SHIFT = 8, |
| 88 | GPIO1D6_MASK = 0xf << GPIO1D6_SHIFT, |
| 89 | GPIO1D6_GPIO = 0, |
| 90 | GPIO1D6_SDMMC_CLK, |
| 91 | |
| 92 | GPIO1D5_SHIFT = 4, |
| 93 | GPIO1D5_MASK = 0xf << GPIO1D5_SHIFT, |
| 94 | GPIO1D5_GPIO = 0, |
| 95 | GPIO1D5_SDMMC_D3, |
| 96 | |
| 97 | GPIO1D4_SHIFT = 0, |
| 98 | GPIO1D4_MASK = 0xf << GPIO1D4_SHIFT, |
| 99 | GPIO1D4_GPIO = 0, |
| 100 | GPIO1D4_SDMMC_D2, |
| 101 | }; |
| 102 | |
| 103 | /* GRF_GPIO2BH_IOMUX */ |
| 104 | enum { |
| 105 | GPIO2B6_SHIFT = 8, |
| 106 | GPIO2B6_MASK = 0xf << GPIO2B6_SHIFT, |
| 107 | GPIO2B6_GPIO = 0, |
| 108 | GPIO2B6_CIF_D1M0, |
| 109 | GPIO2B6_UART2_RXM1, |
| 110 | |
| 111 | GPIO2B4_SHIFT = 0, |
| 112 | GPIO2B4_MASK = 0xf << GPIO2B4_SHIFT, |
| 113 | GPIO2B4_GPIO = 0, |
| 114 | GPIO2B4_CIF_D0M0, |
| 115 | GPIO2B4_UART2_TXM1, |
| 116 | }; |
| 117 | |
| 118 | /* GRF_GPIO3AL_IOMUX */ |
| 119 | enum { |
| 120 | GPIO3A2_SHIFT = 8, |
| 121 | GPIO3A2_MASK = 0xf << GPIO3A2_SHIFT, |
| 122 | GPIO3A2_GPIO = 0, |
| 123 | GPIO3A2_UART5_TX = 4, |
| 124 | |
| 125 | GPIO3A1_SHIFT = 4, |
| 126 | GPIO3A1_MASK = 0xf << GPIO3A1_SHIFT, |
| 127 | GPIO3A1_GPIO = 0, |
| 128 | GPIO3A1_UART5_RX = 4, |
| 129 | }; |
| 130 | |
| 131 | int arch_cpu_init(void) |
| 132 | { |
| 133 | static struct px30_grf * const grf = (void *)GRF_BASE; |
| 134 | u32 __maybe_unused val; |
| 135 | |
| 136 | #ifdef CONFIG_SPL_BUILD |
| 137 | /* We do some SoC one time setting here. */ |
| 138 | /* Disable the ddr secure region setting to make it non-secure */ |
| 139 | writel(0x0, DDR_FW_BASE + FW_DDR_CON); |
| 140 | |
| 141 | /* Set cpu qos priority */ |
| 142 | writel(QOS_PRIORITY_LEVEL(1, 1), SERVICE_CORE_ADDR + QOS_PRIORITY); |
| 143 | |
| 144 | #if !defined(CONFIG_DEBUG_UART_BOARD_INIT) || \ |
| 145 | (CONFIG_DEBUG_UART_BASE != 0xff160000) || \ |
| 146 | (CONFIG_DEBUG_UART_CHANNEL != 0) |
| 147 | /* fix sdmmc pinmux if not using uart2-channel0 as debug uart */ |
| 148 | rk_clrsetreg(&grf->gpio1dl_iomux, |
| 149 | GPIO1D3_MASK | GPIO1D2_MASK, |
| 150 | GPIO1D3_SDMMC_D1 << GPIO1D3_SHIFT | |
| 151 | GPIO1D2_SDMMC_D0 << GPIO1D2_SHIFT); |
| 152 | rk_clrsetreg(&grf->gpio1dh_iomux, |
| 153 | GPIO1D7_MASK | GPIO1D6_MASK | GPIO1D5_MASK | GPIO1D4_MASK, |
| 154 | GPIO1D7_SDMMC_CMD << GPIO1D7_SHIFT | |
| 155 | GPIO1D6_SDMMC_CLK << GPIO1D6_SHIFT | |
| 156 | GPIO1D5_SDMMC_D3 << GPIO1D5_SHIFT | |
| 157 | GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT); |
| 158 | #endif |
| 159 | |
| 160 | #endif |
| 161 | |
| 162 | /* Enable PD_VO (default disable at reset) */ |
| 163 | rk_clrreg(PMU_PWRDN_CON, 1 << 13); |
| 164 | |
| 165 | /* Disable video phy bandgap by default */ |
| 166 | writel(0x82, VIDEO_PHY_BASE + 0x0000); |
| 167 | writel(0x05, VIDEO_PHY_BASE + 0x03ac); |
| 168 | |
| 169 | /* Clear the force_jtag */ |
| 170 | rk_clrreg(&grf->cpu_con[1], 1 << 7); |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
| 175 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT |
| 176 | void board_debug_uart_init(void) |
| 177 | { |
| 178 | static struct px30_grf * const grf = (void *)GRF_BASE; |
| 179 | static struct px30_cru * const cru = (void *)CRU_BASE; |
| 180 | |
| 181 | #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000) |
| 182 | /* uart_sel_clk default select 24MHz */ |
| 183 | rk_clrsetreg(&cru->clksel_con[34], |
| 184 | UART1_PLL_SEL_MASK | UART1_DIV_CON_MASK, |
| 185 | UART1_PLL_SEL_24M << UART1_PLL_SEL_SHIFT | 0); |
| 186 | rk_clrsetreg(&cru->clksel_con[35], |
| 187 | UART1_CLK_SEL_MASK, |
| 188 | UART1_CLK_SEL_UART1 << UART1_CLK_SEL_SHIFT); |
| 189 | |
| 190 | rk_clrsetreg(&grf->gpio1cl_iomux, |
| 191 | GPIO1C1_MASK | GPIO1C0_MASK, |
| 192 | GPIO1C1_UART1_TX << GPIO1C1_SHIFT | |
| 193 | GPIO1C0_UART1_RX << GPIO1C0_SHIFT); |
| 194 | #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000) |
| 195 | /* uart_sel_clk default select 24MHz */ |
| 196 | rk_clrsetreg(&cru->clksel_con[46], |
| 197 | UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, |
| 198 | UART5_PLL_SEL_24M << UART5_PLL_SEL_SHIFT | 0); |
| 199 | rk_clrsetreg(&cru->clksel_con[47], |
| 200 | UART5_CLK_SEL_MASK, |
| 201 | UART5_CLK_SEL_UART5 << UART5_CLK_SEL_SHIFT); |
| 202 | |
| 203 | rk_clrsetreg(&grf->gpio3al_iomux, |
| 204 | GPIO3A2_MASK | GPIO3A1_MASK, |
| 205 | GPIO3A2_UART5_TX << GPIO3A2_SHIFT | |
| 206 | GPIO3A1_UART5_RX << GPIO3A1_SHIFT); |
| 207 | #else |
| 208 | /* GRF_IOFUNC_CON0 */ |
| 209 | enum { |
| 210 | CON_IOMUX_UART2SEL_SHIFT = 10, |
| 211 | CON_IOMUX_UART2SEL_MASK = 3 << CON_IOMUX_UART2SEL_SHIFT, |
| 212 | CON_IOMUX_UART2SEL_M0 = 0, |
| 213 | CON_IOMUX_UART2SEL_M1, |
| 214 | CON_IOMUX_UART2SEL_USBPHY, |
| 215 | }; |
| 216 | |
| 217 | /* uart_sel_clk default select 24MHz */ |
| 218 | rk_clrsetreg(&cru->clksel_con[37], |
| 219 | UART2_PLL_SEL_MASK | UART2_DIV_CON_MASK, |
| 220 | UART2_PLL_SEL_24M << UART2_PLL_SEL_SHIFT | 0); |
| 221 | rk_clrsetreg(&cru->clksel_con[38], |
| 222 | UART2_CLK_SEL_MASK, |
| 223 | UART2_CLK_SEL_UART2 << UART2_CLK_SEL_SHIFT); |
| 224 | |
| 225 | #if (CONFIG_DEBUG_UART2_CHANNEL == 1) |
| 226 | /* Enable early UART2 */ |
| 227 | rk_clrsetreg(&grf->iofunc_con0, |
| 228 | CON_IOMUX_UART2SEL_MASK, |
| 229 | CON_IOMUX_UART2SEL_M1 << CON_IOMUX_UART2SEL_SHIFT); |
| 230 | |
| 231 | rk_clrsetreg(&grf->gpio2bh_iomux, |
| 232 | GPIO2B6_MASK | GPIO2B4_MASK, |
| 233 | GPIO2B6_UART2_RXM1 << GPIO2B6_SHIFT | |
| 234 | GPIO2B4_UART2_TXM1 << GPIO2B4_SHIFT); |
| 235 | #else |
| 236 | rk_clrsetreg(&grf->iofunc_con0, |
| 237 | CON_IOMUX_UART2SEL_MASK, |
| 238 | CON_IOMUX_UART2SEL_M0 << CON_IOMUX_UART2SEL_SHIFT); |
| 239 | |
| 240 | rk_clrsetreg(&grf->gpio1dl_iomux, |
| 241 | GPIO1D3_MASK | GPIO1D2_MASK, |
| 242 | GPIO1D3_UART2_RXM0 << GPIO1D3_SHIFT | |
| 243 | GPIO1D2_UART2_TXM0 << GPIO1D2_SHIFT); |
| 244 | #endif /* CONFIG_DEBUG_UART2_CHANNEL == 1 */ |
| 245 | |
| 246 | #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ |
| 247 | } |
| 248 | #endif /* CONFIG_DEBUG_UART_BOARD_INIT */ |