blob: b1ce014bd55d1bee6f26c0dd53445d57f4511309 [file] [log] [blame]
Martyn Welch56f96e62022-10-25 10:55:02 +01001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Based on vendor support provided by AVNET Embedded
4 *
5 * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
6 * Copyright 2021 General Electric Company
7 * Copyright 2021 Collabora Ltd.
8 */
9
Martyn Welch56f96e62022-10-25 10:55:02 +010010#include <errno.h>
11#include <miiphy.h>
12#include <netdev.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/imx8mp_pins.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/mach-imx/gpio.h>
17#include <asm/mach-imx/iomux-v3.h>
18#include <asm-generic/gpio.h>
19#include <linux/delay.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23static void setup_fec(void)
24{
25 struct iomuxc_gpr_base_regs *gpr =
26 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
27
28 /* Enable RGMII TX clk output */
29 setbits_le32(&gpr->gpr[1], BIT(22));
30}
31
Martyn Welch56f96e62022-10-25 10:55:02 +010032int board_phy_config(struct phy_device *phydev)
33{
34 if (phydev->drv->config)
35 phydev->drv->config(phydev);
36 return 0;
37}
38
39int board_init(void)
40{
41 setup_fec();
42
Martyn Welch56f96e62022-10-25 10:55:02 +010043 return 0;
44}