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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Thomas Abrahamd23cb312016-04-23 22:18:13 +05302/*
3 * Configuration settings for the Espresso7420 board.
4 * Copyright (C) 2016 Samsung Electronics
5 * Thomas Abraham <thomas.ab@samsung.com>
Thomas Abrahamd23cb312016-04-23 22:18:13 +05306 */
7
8#ifndef __CONFIG_EXYNOS7420_COMMON_H
9#define __CONFIG_EXYNOS7420_COMMON_H
10
Thomas Abrahamd23cb312016-04-23 22:18:13 +053011#include <asm/arch/cpu.h> /* get chip and board defs */
12#include <linux/sizes.h>
13
Thomas Abrahamd23cb312016-04-23 22:18:13 +053014/* Miscellaneous configurable options */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053015
Thomas Abrahamd23cb312016-04-23 22:18:13 +053016/* select serial console configuration */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053017
Thomas Abrahamd23cb312016-04-23 22:18:13 +053018/* IRAM Layout */
19#define CONFIG_IRAM_BASE 0x02100000
20#define CONFIG_IRAM_SIZE 0x58000
21#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
Thomas Abrahamf1855fc2016-11-16 18:49:16 +053022#define CPU_RELEASE_ADDR secondary_boot_addr
Thomas Abrahamd23cb312016-04-23 22:18:13 +053023
Thomas Abrahamd23cb312016-04-23 22:18:13 +053024/* select serial console configuration */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053025
Tom Rinibb4dd962022-11-16 13:10:37 -050026#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
Thomas Abrahamd23cb312016-04-23 22:18:13 +053027#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050028#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
Thomas Abrahamd23cb312016-04-23 22:18:13 +053029#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050030#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
Thomas Abrahamd23cb312016-04-23 22:18:13 +053031#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050032#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
Thomas Abrahamd23cb312016-04-23 22:18:13 +053033#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050034#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
Thomas Abrahamd23cb312016-04-23 22:18:13 +053035#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050036#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
Thomas Abrahamd23cb312016-04-23 22:18:13 +053037#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050038#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
Thomas Abrahamd23cb312016-04-23 22:18:13 +053039#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050040#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
Thomas Abrahamd23cb312016-04-23 22:18:13 +053041#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
42
43/* Configuration of ENV Blocks */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053044
45#define BOOT_TARGET_DEVICES(func) \
46 func(MMC, mmc, 1) \
47 func(MMC, mmc, 0) \
48
49#ifndef MEM_LAYOUT_ENV_SETTINGS
50#define MEM_LAYOUT_ENV_SETTINGS \
51 "bootm_size=0x10000000\0" \
52 "kernel_addr_r=0x42000000\0" \
53 "fdt_addr_r=0x43000000\0" \
54 "ramdisk_addr_r=0x43300000\0" \
55 "scriptaddr=0x50000000\0" \
56 "pxefile_addr_r=0x51000000\0"
57#endif
58
59#ifndef EXYNOS_DEVICE_SETTINGS
60#define EXYNOS_DEVICE_SETTINGS \
61 "stdin=serial\0" \
62 "stdout=serial\0" \
63 "stderr=serial\0"
64#endif
65
66#ifndef EXYNOS_FDTFILE_SETTING
67#define EXYNOS_FDTFILE_SETTING
68#endif
69
70#define CONFIG_EXTRA_ENV_SETTINGS \
71 EXYNOS_DEVICE_SETTINGS \
72 EXYNOS_FDTFILE_SETTING \
73 MEM_LAYOUT_ENV_SETTINGS
74
75#endif /* __CONFIG_EXYNOS7420_COMMON_H */