blob: 9392facfa88169ff8177f8e7c3341baed082a493 [file] [log] [blame]
Angelo Dureghelloc6164c92019-03-13 21:46:41 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
4 */
5
6/ {
7 compatible = "fsl,mcf5208";
8
9 aliases {
10 serial0 = &uart0;
Angelo Durgehelloc6e17f92019-11-15 23:54:12 +010011 fec0 = &fec0;
Angelo Dureghelloc6164c92019-03-13 21:46:41 +010012 };
13
14 soc {
15 compatible = "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 uart0: uart@fc060000 {
20 compatible = "fsl,mcf-uart";
21 reg = <0xfc060000 0x40>;
22 status = "disabled";
23 };
24
25 uart1: uart@fc064000 {
26 compatible = "fsl,mcf-uart";
27 reg = <0xfc064000 0x40>;
28 status = "disabled";
29 };
30
31 uart2: uart@fc068000 {
32 compatible = "fsl,mcf-uart";
33 reg = <0xfc068000 0x40>;
34 status = "disabled";
35 };
Angelo Durgehelloc6e17f92019-11-15 23:54:12 +010036
37 fec0: ethernet@fc030000 {
38 compatible = "fsl,mcf-fec";
39 reg = <0xfc030000 0x400>;
40 mii-base = <0>;
41 max-speed = <100>;
42 timeout-loop = <50000>;
43 status = "disabled";
44 };
Angelo Dureghellod768df12023-04-05 00:59:27 +020045
46 i2c0: i2c@fc058000 {
47 compatible = "fsl-i2c";
48 #address-cells=<1>;
49 #size-cells=<0>;
50 cell-index = <0>;
51 reg = <0xfc058000 0x14>;
52 clock-frequency = <100000>;
53 status = "disabled";
54 };
Angelo Dureghelloc6164c92019-03-13 21:46:41 +010055 };
56};