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Mike Frysinger94bae5c2008-03-30 15:46:13 -04001/*
2 * serial.h - common serial defines for early debug and serial driver.
3 * any functions defined here must be always_inline since
4 * initcode cannot have function calls.
5 *
6 * Copyright (c) 2004-2007 Analog Devices Inc.
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#ifndef __BFIN_CPU_SERIAL_H__
12#define __BFIN_CPU_SERIAL_H__
13
14#include <asm/blackfin.h>
15#include <asm/mach-common/bits/uart.h>
16
Mike Frysinger500f2bb2008-10-11 21:52:17 -040017#ifndef CONFIG_UART_CONSOLE
18# define CONFIG_UART_CONSOLE 0
19#endif
20
Mike Frysinger94bae5c2008-03-30 15:46:13 -040021#ifdef CONFIG_DEBUG_EARLY_SERIAL
22# define BFIN_DEBUG_EARLY_SERIAL 1
23#else
24# define BFIN_DEBUG_EARLY_SERIAL 0
25#endif
26
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050027#ifndef __ASSEMBLY__
28
Mike Frysinger946550d2010-06-02 06:00:27 -040029#include <asm/portmux.h>
30
Mike Frysinger94bae5c2008-03-30 15:46:13 -040031#define LOB(x) ((x) & 0xFF)
32#define HIB(x) (((x) >> 8) & 0xFF)
33
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050034/*
35 * All Blackfin system MMRs are padded to 32bits even if the register
36 * itself is only 16bits. So use a helper macro to streamline this.
37 */
38#define __BFP(m) u16 m; u16 __pad_##m
39struct bfin_mmr_serial {
40#ifdef __ADSPBF54x__
41 __BFP(dll);
42 __BFP(dlh);
43 __BFP(gctl);
44 __BFP(lcr);
45 __BFP(mcr);
46 __BFP(lsr);
47 __BFP(msr);
48 __BFP(scr);
49 __BFP(ier_set);
50 __BFP(ier_clear);
51 __BFP(thr);
52 __BFP(rbr);
53#else
54 union {
55 u16 dll;
56 u16 thr;
57 const u16 rbr;
58 };
59 const u16 __spad0;
60 union {
61 u16 dlh;
62 u16 ier;
63 };
64 const u16 __spad1;
65 const __BFP(iir);
66 __BFP(lcr);
67 __BFP(mcr);
68 __BFP(lsr);
69 __BFP(msr);
70 __BFP(scr);
71 const u32 __spad2;
72 __BFP(gctl);
73#endif
74};
75#undef __BFP
76
Mike Frysingerfbd8ae42010-12-17 16:23:59 -050077#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
78#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
79#define MMR_UART(mmr) _PASTE_UART(CONFIG_UART_CONSOLE, UART, DLL)
80#define P_UART(pin) _PASTE_UART(CONFIG_UART_CONSOLE, P_UART, pin)
81
82#ifndef UART_DLL
83# define UART_DLL MMR_UART(DLL)
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050084#else
85# if CONFIG_UART_CONSOLE != 0
86# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
Mike Frysinger94bae5c2008-03-30 15:46:13 -040087# endif
88#endif
Mike Frysingerfbd8ae42010-12-17 16:23:59 -050089#define pUART ((volatile struct bfin_mmr_serial *)UART_DLL)
Mike Frysinger94bae5c2008-03-30 15:46:13 -040090
Mike Frysinger94bae5c2008-03-30 15:46:13 -040091#ifdef __ADSPBF54x__
92# define ACCESS_LATCH()
93# define ACCESS_PORT_IER()
Mike Frysinger94bae5c2008-03-30 15:46:13 -040094#else
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -050095# define ACCESS_LATCH() \
96 bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB)
97# define ACCESS_PORT_IER() \
98 bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB)
Mike Frysinger94bae5c2008-03-30 15:46:13 -040099#endif
100
101__attribute__((always_inline))
102static inline void serial_do_portmux(void)
103{
Mike Frysinger946550d2010-06-02 06:00:27 -0400104 if (!BFIN_DEBUG_EARLY_SERIAL) {
Mike Frysingerfbd8ae42010-12-17 16:23:59 -0500105 const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, };
Mike Frysinger946550d2010-06-02 06:00:27 -0400106 peripheral_request_list(pins, "bfin-uart");
107 return;
108 }
109
Mike Frysinger07374482008-10-11 21:15:53 -0400110#if defined(__ADSPBF51x__)
111# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
112 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \
113 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
114 switch (CONFIG_UART_CONSOLE) {
115 case 0: DO_MUX(G, 5, 5, 9, 10); break; /* Port G; mux 5; PG9 and PG10 */
116 case 1: DO_MUX(F, 2, 3, 14, 15); break; /* Port H; mux 2/3; PH14 and PH15 */
117 }
118 SSYNC();
119#elif defined(__ADSPBF52x__)
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400120# define DO_MUX(port, mux, tx, rx) \
121 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \
122 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
123 switch (CONFIG_UART_CONSOLE) {
124 case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */
125 case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */
126 }
127 SSYNC();
128#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
Mike Frysingerfbd8ae42010-12-17 16:23:59 -0500129 const uint16_t func[] = { PFDE, PFTE, };
130 bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
131 bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
132 (1 << P_IDENT(P_UART(RX))) |
133 (1 << P_IDENT(P_UART(TX))));
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400134 SSYNC();
135#elif defined(__ADSPBF54x__)
136# define DO_MUX(port, tx, rx) \
137 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \
138 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
139 switch (CONFIG_UART_CONSOLE) {
140 case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */
141 case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */
142 case 2: DO_MUX(B, 4, 5); break; /* Port B; PB4 and PB5 */
143 case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */
144 }
145 SSYNC();
Mike Frysingerfbd8ae42010-12-17 16:23:59 -0500146#elif defined(__ADSPBF561__)
147 /* UART pins could be GPIO, but they aren't pin muxed. */
148#else
149# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
150# error "missing portmux logic for UART"
151# endif
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400152#endif
153}
154
155__attribute__((always_inline))
156static inline void serial_early_init(void)
157{
158 /* handle portmux crap on different Blackfins */
159 serial_do_portmux();
160
Mike Frysingercad68e12009-04-04 09:10:27 -0400161 /* always enable UART -- avoids anomalies 05000309 and 05000350 */
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500162 bfin_write16(&pUART->gctl, UCEN);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400163
164 /* Set LCR to Word Lengh 8-bit word select */
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500165 bfin_write16(&pUART->lcr, WLS_8);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400166
167 SSYNC();
168}
169
170__attribute__((always_inline))
Mike Frysinger84451302008-12-10 12:33:54 -0500171static inline void serial_early_put_div(uint16_t divisor)
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400172{
Mike Frysinger84451302008-12-10 12:33:54 -0500173 /* Set DLAB in LCR to Access DLL and DLH */
174 ACCESS_LATCH();
175 SSYNC();
176
177 /* Program the divisor to get the baud rate we want */
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500178 bfin_write16(&pUART->dll, LOB(divisor));
179 bfin_write16(&pUART->dlh, HIB(divisor));
Mike Frysinger84451302008-12-10 12:33:54 -0500180 SSYNC();
181
182 /* Clear DLAB in LCR to Access THR RBR IER */
183 ACCESS_PORT_IER();
184 SSYNC();
185}
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400186
Mike Frysinger84451302008-12-10 12:33:54 -0500187__attribute__((always_inline))
188static inline uint16_t serial_early_get_div(void)
189{
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400190 /* Set DLAB in LCR to Access DLL and DLH */
191 ACCESS_LATCH();
192 SSYNC();
193
Mike Frysinger3b7ed5a2009-11-12 18:42:53 -0500194 uint8_t dll = bfin_read16(&pUART->dll);
195 uint8_t dlh = bfin_read16(&pUART->dlh);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400196 uint16_t divisor = (dlh << 8) | dll;
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400197
198 /* Clear DLAB in LCR to Access THR RBR IER */
199 ACCESS_PORT_IER();
200 SSYNC();
201
Mike Frysinger84451302008-12-10 12:33:54 -0500202 return divisor;
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400203}
204
Mike Frysingercca6b792009-04-24 23:54:19 -0400205/* We cannot use get_sclk() early on as it uses caches in external memory */
206#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
207# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
208#endif
209
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400210__attribute__((always_inline))
211static inline void serial_early_set_baud(uint32_t baud)
212{
Mike Frysingerae2d4672008-04-20 03:11:53 -0400213 /* Translate from baud into divisor in terms of SCLK. The
214 * weird multiplication is to make sure we over sample just
215 * a little rather than under sample the incoming signals.
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400216 */
Mike Frysinger84451302008-12-10 12:33:54 -0500217 serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400218}
219
220#ifndef BFIN_IN_INITCODE
221__attribute__((always_inline))
222static inline void serial_early_puts(const char *s)
223{
224 if (BFIN_DEBUG_EARLY_SERIAL) {
225 serial_puts("Early: ");
226 serial_puts(s);
227 }
228}
229#endif
230
231#else
232
233.macro serial_early_init
234#ifdef CONFIG_DEBUG_EARLY_SERIAL
235 call _serial_initialize;
236#endif
237.endm
238
239.macro serial_early_set_baud
240#ifdef CONFIG_DEBUG_EARLY_SERIAL
241 R0.L = LO(CONFIG_BAUDRATE);
242 R0.H = HI(CONFIG_BAUDRATE);
243 call _serial_set_baud;
244#endif
245.endm
246
Mike Frysinger94bae5c2008-03-30 15:46:13 -0400247/* Since we embed the string right into our .text section, we need
248 * to find its address. We do this by getting our PC and adding 2
249 * bytes (which is the length of the jump instruction). Then we
250 * pass this address to serial_puts().
251 */
252#ifdef CONFIG_DEBUG_EARLY_SERIAL
253# define serial_early_puts(str) \
254 call _get_pc; \
255 jump 1f; \
256 .ascii "Early:"; \
257 .ascii __FILE__; \
258 .ascii ": "; \
259 .ascii str; \
260 .asciz "\n"; \
261 .align 4; \
2621: \
263 R0 += 2; \
264 call _serial_puts;
265#else
266# define serial_early_puts(str)
267#endif
268
269#endif
270
271#endif