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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Timur Tabi054838e2006-10-31 18:44:42 -06002/*
Kumar Gala6a6d9482009-07-28 21:49:52 -05003 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Timur Tabi054838e2006-10-31 18:44:42 -06004 */
5
6/*
Timur Tabi435e3a72007-01-31 15:54:29 -06007 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi054838e2006-10-31 18:44:42 -06008
9 Memory map:
10
11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi435e3a72007-01-31 15:54:29 -060017 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi054838e2006-10-31 18:44:42 -060018 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi435e3a72007-01-31 15:54:29 -060019 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi054838e2006-10-31 18:44:42 -060022
23 I2C address list:
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +010024 Align. Board
25 Bus Addr Part No. Description Length Location
Timur Tabi054838e2006-10-31 18:44:42 -060026 ----------------------------------------------------------------
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +010027 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi054838e2006-10-31 18:44:42 -060028
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +010029 I2C1 0x20 PCF8574 I2C Expander 0 U8
30 I2C1 0x21 PCF8574 I2C Expander 0 U10
31 I2C1 0x38 PCF8574A I2C Expander 0 U8
32 I2C1 0x39 PCF8574A I2C Expander 0 U10
33 I2C1 0x51 (DDR) DDR EEPROM 1 U1
34 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi054838e2006-10-31 18:44:42 -060035
36 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
37*/
38
39#ifndef __CONFIG_H
40#define __CONFIG_H
41
Timur Tabi3e1d49a2008-02-08 13:15:55 -060042#define CONFIG_MISC_INIT_F
Timur Tabi435e3a72007-01-31 15:54:29 -060043
Timur Tabi3e1d49a2008-02-08 13:15:55 -060044/*
45 * On-board devices
46 */
Timur Tabi435e3a72007-01-31 15:54:29 -060047
Mario Six5bb7f752019-01-21 09:17:44 +010048#ifdef CONFIG_TARGET_MPC8349ITX
Joe Hershberger2ce021f2011-10-11 23:57:15 -050049/* The CF card interface on the back of the board */
50#define CONFIG_COMPACT_FLASH
Timur Tabi3e1d49a2008-02-08 13:15:55 -060051#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
Valeriy Glushkovce9d5852009-06-30 15:48:41 +030052#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
Timur Tabi435e3a72007-01-31 15:54:29 -060053#endif
Timur Tabi054838e2006-10-31 18:44:42 -060054
Timur Tabi435e3a72007-01-31 15:54:29 -060055#define CONFIG_RTC_DS1337
Heiko Schocherf2850742012-10-24 13:48:22 +020056#define CONFIG_SYS_I2C
Timur Tabi054838e2006-10-31 18:44:42 -060057
Timur Tabi435e3a72007-01-31 15:54:29 -060058/*
59 * Device configurations
60 */
61
62/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +020063#ifdef CONFIG_SYS_I2C
64#define CONFIG_SYS_I2C_FSL
65#define CONFIG_SYS_FSL_I2C_SPEED 400000
66#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
67#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
68#define CONFIG_SYS_FSL_I2C2_SPEED 400000
69#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
70#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabi054838e2006-10-31 18:44:42 -060071
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Valeriy Glushkov3da9bbf2009-02-04 18:27:49 +020073#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
Timur Tabi054838e2006-10-31 18:44:42 -060074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
76#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
77#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
78#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
79#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
Joe Hershberger2ce021f2011-10-11 23:57:15 -050080#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
81#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi054838e2006-10-31 18:44:42 -060082
Timur Tabi054838e2006-10-31 18:44:42 -060083/* Don't probe these addresses: */
Joe Hershberger2ce021f2011-10-11 23:57:15 -050084#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
86 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
Joe Hershberger2ce021f2011-10-11 23:57:15 -050087 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
Timur Tabi054838e2006-10-31 18:44:42 -060088/* Bit definitions for the 8574[A] I2C expander */
Joe Hershberger2ce021f2011-10-11 23:57:15 -050089 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
90#define I2C_8574_REVISION 0x03
Timur Tabi054838e2006-10-31 18:44:42 -060091#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
92#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
93#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
94#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
95
Timur Tabi054838e2006-10-31 18:44:42 -060096#endif
97
Timur Tabi435e3a72007-01-31 15:54:29 -060098/* Compact Flash */
99#ifdef CONFIG_COMPACT_FLASH
Timur Tabi054838e2006-10-31 18:44:42 -0600100
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_SYS_IDE_MAXBUS 1
102#define CONFIG_SYS_IDE_MAXDEVICE 1
Timur Tabi054838e2006-10-31 18:44:42 -0600103
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
105#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
106#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
107#define CONFIG_SYS_ATA_REG_OFFSET 0
108#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
109#define CONFIG_SYS_ATA_STRIDE 2
Timur Tabi054838e2006-10-31 18:44:42 -0600110
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500111/* If a CF card is not inserted, time out quickly */
112#define ATA_RESET_TIME 1
Timur Tabi054838e2006-10-31 18:44:42 -0600113
Valeriy Glushkove3418772009-02-05 14:35:21 +0200114#endif
115
116/*
117 * SATA
118 */
119#ifdef CONFIG_SATA_SIL3114
120
121#define CONFIG_SYS_SATA_MAX_DEVICE 4
Valeriy Glushkove3418772009-02-05 14:35:21 +0200122#define CONFIG_LBA48
Timur Tabi054838e2006-10-31 18:44:42 -0600123
Timur Tabi435e3a72007-01-31 15:54:29 -0600124#endif
Timur Tabi054838e2006-10-31 18:44:42 -0600125
Valeriy Glushkovce9d5852009-06-30 15:48:41 +0300126#ifdef CONFIG_SYS_USB_HOST
127/*
128 * Support USB
129 */
Valeriy Glushkovce9d5852009-06-30 15:48:41 +0300130#define CONFIG_USB_EHCI_FSL
131
132/* Current USB implementation supports the only USB controller,
133 * so we have to choose between the MPH or the DR ones */
134#if 1
135#define CONFIG_HAS_FSL_MPH_USB
136#else
137#define CONFIG_HAS_FSL_DR_USB
138#endif
139
140#endif
141
Timur Tabi054838e2006-10-31 18:44:42 -0600142/*
Timur Tabi435e3a72007-01-31 15:54:29 -0600143 * DDR Setup
Timur Tabi054838e2006-10-31 18:44:42 -0600144 */
Mario Sixc9f92772019-01-21 09:18:15 +0100145#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500147#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_MEMTEST_END 0x2000
Timur Tabi054838e2006-10-31 18:44:42 -0600149
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500150#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
151 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Timur Tabi83d47822007-04-30 13:59:50 -0500152
Valeriy Glushkov3da9bbf2009-02-04 18:27:49 +0200153#define CONFIG_VERY_BIG_RAM
154#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
155
Heiko Schocherf2850742012-10-24 13:48:22 +0200156#ifdef CONFIG_SYS_I2C
Timur Tabi435e3a72007-01-31 15:54:29 -0600157#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
158#endif
159
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500160/* No SPD? Then manually set up DDR parameters */
161#ifndef CONFIG_SPD_EEPROM
162 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
Joe Hershberger5ade3902011-10-11 23:57:31 -0500163 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500164 | CSCONFIG_ROW_BIT_13 \
165 | CSCONFIG_COL_BIT_10)
Timur Tabi054838e2006-10-31 18:44:42 -0600166
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
168 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
Timur Tabi054838e2006-10-31 18:44:42 -0600169#endif
170
Timur Tabi435e3a72007-01-31 15:54:29 -0600171/*
172 *Flash on the Local Bus
173 */
174
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
176#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500177/* 127 64KB sectors + 8 8KB sectors per device */
178#define CONFIG_SYS_MAX_FLASH_SECT 135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
181#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Timur Tabi435e3a72007-01-31 15:54:29 -0600182
183/* The ITX has two flash chips, but the ITX-GP has only one. To support both
184boards, we say we have two, but don't display a message if we find only one. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_QUIET_TEST
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500186#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
187#define CONFIG_SYS_FLASH_BANKS_LIST \
188 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
189#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
Timur Tabi435e3a72007-01-31 15:54:29 -0600190
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600191/* Vitesse 7385 */
192
193#ifdef CONFIG_VSC7385_ENET
194
195#define CONFIG_TSEC2
196
197/* The flash address and size of the VSC7385 firmware image */
198#define CONFIG_VSC7385_IMAGE 0xFEFFE000
199#define CONFIG_VSC7385_IMAGE_SIZE 8192
200
201#endif
202
Timur Tabi435e3a72007-01-31 15:54:29 -0600203/*
204 * BRx, ORx, LBLAWBARx, and LBLAWARx
205 */
206
Timur Tabi054838e2006-10-31 18:44:42 -0600207
Timur Tabi435e3a72007-01-31 15:54:29 -0600208/* Vitesse 7385 */
Timur Tabi054838e2006-10-31 18:44:42 -0600209
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_VSC7385_BASE 0xF8000000
Timur Tabi054838e2006-10-31 18:44:42 -0600211
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600212#ifdef CONFIG_VSC7385_ENET
213
Mario Sixc1e29d92019-01-21 09:18:01 +0100214
Timur Tabi435e3a72007-01-31 15:54:29 -0600215#endif
216
Timur Tabi054838e2006-10-31 18:44:42 -0600217
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500218#define CONFIG_SYS_LED_BASE 0xF9000000
Mario Sixc1e29d92019-01-21 09:18:01 +0100219
Timur Tabi435e3a72007-01-31 15:54:29 -0600220
221/* Compact Flash */
Timur Tabi054838e2006-10-31 18:44:42 -0600222
223#ifdef CONFIG_COMPACT_FLASH
224
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500225#define CONFIG_SYS_CF_BASE 0xF0000000
Timur Tabi054838e2006-10-31 18:44:42 -0600226
Timur Tabi054838e2006-10-31 18:44:42 -0600227
Timur Tabi054838e2006-10-31 18:44:42 -0600228#endif
229
Timur Tabi435e3a72007-01-31 15:54:29 -0600230/*
231 * U-Boot memory configuration
232 */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200233#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Timur Tabi054838e2006-10-31 18:44:42 -0600234
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200235#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
236#define CONFIG_SYS_RAMBOOT
Timur Tabi054838e2006-10-31 18:44:42 -0600237#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#undef CONFIG_SYS_RAMBOOT
Timur Tabi054838e2006-10-31 18:44:42 -0600239#endif
240
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200241#define CONFIG_SYS_INIT_RAM_LOCK
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500242#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
243#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Timur Tabi054838e2006-10-31 18:44:42 -0600244
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500245#define CONFIG_SYS_GBL_DATA_OFFSET \
246 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Timur Tabi054838e2006-10-31 18:44:42 -0600248
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao349a0152016-07-08 11:25:14 +0800250#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Kim Phillips831d2f62012-06-30 18:29:20 -0500251#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Timur Tabi054838e2006-10-31 18:44:42 -0600252
253/*
Timur Tabi054838e2006-10-31 18:44:42 -0600254 * Serial Port
255 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200256#define CONFIG_SYS_NS16550_SERIAL
257#define CONFIG_SYS_NS16550_REG_SIZE 1
258#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Timur Tabi054838e2006-10-31 18:44:42 -0600259
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200260#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500261 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Timur Tabi435e3a72007-01-31 15:54:29 -0600262
Simon Glassa406b692016-10-17 20:12:38 -0600263#define CONSOLE ttyS0
Timur Tabi054838e2006-10-31 18:44:42 -0600264
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
266#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Timur Tabi054838e2006-10-31 18:44:42 -0600267
Timur Tabi435e3a72007-01-31 15:54:29 -0600268/*
269 * PCI
270 */
Timur Tabi054838e2006-10-31 18:44:42 -0600271#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000272#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabi054838e2006-10-31 18:44:42 -0600273
274#define CONFIG_MPC83XX_PCI2
275
276/*
277 * General PCI
278 * Addresses are mapped 1-1.
279 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200280#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
281#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
282#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500283#define CONFIG_SYS_PCI1_MMIO_BASE \
284 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200285#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
286#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500287#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
288#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
289#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Timur Tabi054838e2006-10-31 18:44:42 -0600290
291#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500292#define CONFIG_SYS_PCI2_MEM_BASE \
293 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
295#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500296#define CONFIG_SYS_PCI2_MMIO_BASE \
297 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200298#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
299#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500300#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
301#define CONFIG_SYS_PCI2_IO_PHYS \
302 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
303#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Timur Tabi054838e2006-10-31 18:44:42 -0600304#endif
305
Timur Tabi054838e2006-10-31 18:44:42 -0600306#ifndef CONFIG_PCI_PNP
307 #define PCI_ENET0_IOADDR 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200308 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
Timur Tabi054838e2006-10-31 18:44:42 -0600309 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
310#endif
311
312#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
313
314#endif
315
316/* TSEC */
317
318#ifdef CONFIG_TSEC_ENET
Kim Phillips177e58f2007-05-16 16:52:19 -0500319#define CONFIG_TSEC1
Timur Tabi054838e2006-10-31 18:44:42 -0600320
Kim Phillips177e58f2007-05-16 16:52:19 -0500321#ifdef CONFIG_TSEC1
Andy Fleming458c3892007-08-16 16:35:02 -0500322#define CONFIG_HAS_ETH0
Kim Phillips177e58f2007-05-16 16:52:19 -0500323#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200324#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100325#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi054838e2006-10-31 18:44:42 -0600326#define TSEC1_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500327#define TSEC1_FLAGS TSEC_GIGABIT
Timur Tabi054838e2006-10-31 18:44:42 -0600328#endif
329
Kim Phillips177e58f2007-05-16 16:52:19 -0500330#ifdef CONFIG_TSEC2
Timur Tabi435e3a72007-01-31 15:54:29 -0600331#define CONFIG_HAS_ETH1
Kim Phillips177e58f2007-05-16 16:52:19 -0500332#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200333#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi3e1d49a2008-02-08 13:15:55 -0600334
Timur Tabi054838e2006-10-31 18:44:42 -0600335#define TSEC2_PHY_ADDR 4
336#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500337#define TSEC2_FLAGS TSEC_GIGABIT
Timur Tabi054838e2006-10-31 18:44:42 -0600338#endif
339
340#define CONFIG_ETHPRIME "Freescale TSEC"
341
342#endif
343
Timur Tabi054838e2006-10-31 18:44:42 -0600344/*
345 * Environment
346 */
Timur Tabi435e3a72007-01-31 15:54:29 -0600347#define CONFIG_ENV_OVERWRITE
348
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200349#ifndef CONFIG_SYS_RAMBOOT
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500350 #define CONFIG_ENV_ADDR \
351 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200352 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500353 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi054838e2006-10-31 18:44:42 -0600354#else
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500355 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
356 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi054838e2006-10-31 18:44:42 -0600357#endif
358
359#define CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200360#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
Timur Tabi054838e2006-10-31 18:44:42 -0600361
Jon Loeliger3b7116d2007-07-04 22:30:06 -0500362/*
Jon Loeligered26c742007-07-10 09:10:49 -0500363 * BOOTP options
364 */
365#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeligered26c742007-07-10 09:10:49 -0500366
Timur Tabi054838e2006-10-31 18:44:42 -0600367/* Watchdog */
Timur Tabi054838e2006-10-31 18:44:42 -0600368#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi054838e2006-10-31 18:44:42 -0600369
370/*
371 * Miscellaneous configurable options
372 */
Timur Tabi435e3a72007-01-31 15:54:29 -0600373
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200374#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips73060b52009-08-26 21:27:37 -0500375#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Timur Tabi435e3a72007-01-31 15:54:29 -0600376
Timur Tabi054838e2006-10-31 18:44:42 -0600377/*
378 * For booting Linux, the board info and command line data
Ira W. Snyderc5a22d02010-09-10 15:42:32 -0700379 * have to be in the first 256 MB of memory, since this is
Timur Tabi054838e2006-10-31 18:44:42 -0600380 * the maximum mapped by the Linux kernel during initialization.
381 */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500382 /* Initial Memory map for Linux*/
383#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao9c747962016-07-08 11:25:15 +0800384#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabi054838e2006-10-31 18:44:42 -0600385
Timur Tabi435e3a72007-01-31 15:54:29 -0600386/*
387 * System performance
388 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200389#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
390#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Valeriy Glushkovce9d5852009-06-30 15:48:41 +0300391#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
392#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
Timur Tabi054838e2006-10-31 18:44:42 -0600393
Timur Tabi435e3a72007-01-31 15:54:29 -0600394/*
395 * System IO Config
396 */
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500397/* Needed for gigabit to work on TSEC 1 */
398#define CONFIG_SYS_SICRH SICRH_TSOBI1
399 /* USB DR as device + USB MPH as host */
400#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
Timur Tabi054838e2006-10-31 18:44:42 -0600401
Jon Loeliger3b7116d2007-07-04 22:30:06 -0500402#if defined(CONFIG_CMD_KGDB)
Timur Tabi054838e2006-10-31 18:44:42 -0600403#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Timur Tabi054838e2006-10-31 18:44:42 -0600404#endif
405
Timur Tabi054838e2006-10-31 18:44:42 -0600406/*
407 * Environment Configuration
408 */
409#define CONFIG_ENV_OVERWRITE
410
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500411#define CONFIG_NETDEV "eth0"
Timur Tabi054838e2006-10-31 18:44:42 -0600412
Timur Tabi435e3a72007-01-31 15:54:29 -0600413/* Default path and filenames */
Joe Hershberger257ff782011-10-13 13:03:47 +0000414#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000415#define CONFIG_BOOTFILE "uImage"
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500416 /* U-Boot image on TFTP server */
417#define CONFIG_UBOOTPATH "u-boot.bin"
Timur Tabi054838e2006-10-31 18:44:42 -0600418
Mario Six5bb7f752019-01-21 09:17:44 +0100419#ifdef CONFIG_TARGET_MPC8349ITX
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500420#define CONFIG_FDTFILE "mpc8349emitx.dtb"
Timur Tabi054838e2006-10-31 18:44:42 -0600421#else
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500422#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
Timur Tabi054838e2006-10-31 18:44:42 -0600423#endif
424
Timur Tabi435e3a72007-01-31 15:54:29 -0600425
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100426#define CONFIG_EXTRA_ENV_SETTINGS \
Simon Glassa406b692016-10-17 20:12:38 -0600427 "console=" __stringify(CONSOLE) "\0" \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500428 "netdev=" CONFIG_NETDEV "\0" \
429 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denka1be4762008-05-20 16:00:29 +0200430 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200431 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
432 " +$filesize; " \
433 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
434 " +$filesize; " \
435 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
436 " $filesize; " \
437 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
438 " +$filesize; " \
439 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
440 " $filesize\0" \
Kim Phillips73060b52009-08-26 21:27:37 -0500441 "fdtaddr=780000\0" \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500442 "fdtfile=" CONFIG_FDTFILE "\0"
Kim Phillips774e1b52006-11-01 00:10:40 -0600443
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100444#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi435e3a72007-01-31 15:54:29 -0600445 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
Joe Hershberger2ce021f2011-10-11 23:57:15 -0500446 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
Timur Tabi435e3a72007-01-31 15:54:29 -0600447 " console=$console,$baudrate $othbootargs; " \
448 "tftp $loadaddr $bootfile;" \
449 "tftp $fdtaddr $fdtfile;" \
450 "bootm $loadaddr - $fdtaddr"
Kim Phillips774e1b52006-11-01 00:10:40 -0600451
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100452#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi435e3a72007-01-31 15:54:29 -0600453 "setenv bootargs root=/dev/ram rw" \
454 " console=$console,$baudrate $othbootargs; " \
455 "tftp $ramdiskaddr $ramdiskfile;" \
456 "tftp $loadaddr $bootfile;" \
457 "tftp $fdtaddr $fdtfile;" \
458 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi054838e2006-10-31 18:44:42 -0600459
Timur Tabi054838e2006-10-31 18:44:42 -0600460#endif