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wdenk5da7f2f2004-01-03 00:43:19 +00001This file contains status information for the port of the U-Boot to the Marvell Development Board DB64360.
2
3Author: Ronen Shitrit <rshitrit@il.marvell.com>
4
5This U-Boot version is based on the work of Brian Waite and his team from Sky Computers, THANKS A LOT.
6
7Supported CPU Types :
8+++++++++++++++++++++
9 IBM750FX (ver 2.3)
10 MPC7455 (ver 2.1)
11
12Supported CPU Cache Library:
13++++++++++++++++++++++++++++
14 L1 and L2 only.
15
16CPU Control:
17++++++++++++
18 Marvell optimized CPU control settings:
19 Big Endian
20 Enable CPU pipeline
21 Data and address parity checking
22 AACK# assert after 2 cycles
23
24U-Boot I/O Interface Support:
25+++++++++++++++++++++++++++++
26- Serial Interface (UART)
27 This version of U-Boot supports the SIO U-Boot interface driver, with a PC standard baud rate up to 115200 BPS on the ST16C2552 DUART device located on DB-64360-BP device module.
28- Network Interface
29 This LSP supports the following network devices:
30 o MV64360 Gigabit Ethernet Controller device
31 o Intel 82559 PCI NIC device
32- PCI Interface
33 This LSP supports the following capabilities over the Marvell(r) device PCI0/1 units:
34 o Local PCI configuration header control.
35 o External PCI configuration header control (for other agents on the bus).
36 o PCI configuration application. Scans and configures the PCI agents on the bus.
37 o PCI Internal Arbiter activation and configuration.
38
39Memory Interface Support:
40+++++++++++++++++++++++++
41- DDR
42 o DDR auto-detection and configuration. Enables access up to 256 MB, due to the limitations of using only four Base Address Translations (BATs).
43 o Enable DDR ECC in case both DIMM support ECC, and initialize the entire DDR memory by using the idma.
44
45- Devices
46 o Initializes the MV64360 device's chip-selects 0-3 to enable access to the boot flash, main flash, real time clock (RTC), and external SRAM.
47 o JFFS2
48 JFFS2 is a crash/power down safe file system for disk-less embedded devices.
49 This version of U-Boot supports scanning a JFFS2 file system on the large flash and loading files from it.
50
51Unsupported Features:
52+++++++++++++++++++++
53 Messaging unit - No support for MV64360 Messaging unit.
54 Watchdog Timer - No support for MV64360 Watchdog unit.
55 L3 cache - No support for L3 cache on MPC7455
56 Dual PCU - No support for Dual CPU
57 PCI-X was never tested
58 IDMA driver - No support for MV64360 IDMA unit.
59
60BSP Special Considerations:
61+++++++++++++++++++++++++++
62- DDR DIMM location: Due to PCI specifications, place the larger DIMM module in the MAIN DIMM slot, in order to have full access from the PCI to the DDR while using both DDR slots.
63- DDR DIMM types: Due to architectural and software limitations, the registration, CAS Latency, and ECC of both DIMMS should be identical.
64
65Test Cases:
66###########
67UART:
68+++++
69Check that the UART baud rate is configured to 57600 and 115200, and check:
70 Transmit (to the hyper terminal) and Receive (using the keyboard) using Linux minicom.
71 Load S-Record file over the UART using Windows HyperTerminal.
72
73Network:
74++++++++
75Use TFTP application to load a debugged executable and execute it.
76Insert Intel PCI NIC 82557 rev 08 to PCI slots 0-3 Check correct detection of the PCI NIC, correct configuration of the NIC BARs , and load files by using tftp through the PCI NIC.
77
78Memory:
79+++++++
80Test DDR DIMMs on DB-64360-BP. See that Uboot report their correct parameters:
81o 128MB DIMM consist of 16 x 64Mbit devices
82o 128MB DIMM consist of 09 x 128Mbit devices @ 266MHz.
83o 256MB DIMM consist of 16 x 128Mbit devices @ 266MHz.
84o 256MB DIMM consist of 09 x 256Mbit devices @ 400MHz.
85o 512MB DIMM consist of 16 x 256Mbit devices @ 333MHz.
86o 512MB DIMM consist of 18 x 256Mbit devices @ 266MHz.
87o GigaB DIMM consist of 36 x 256Mbit devices @ 266MHz registered
88
89For each chip select device perform data access to verify its accessibility.
90
91Create a JFFS2 on the large flash through the Linux holding few files, few dirs and a uImage.
92Load the U-Boot and:
93use the ls command to check correct scan of the JFFS2 on the large flash.
94Use the floads command to copy the uImage from the JFFS2 on the large flash to the DIMM SDRAM, and boot the uImage.
95
96PCI:
97++++
981)Insert different PCI cards:
99Galileo 64120A rev 10 and 12, Intel Nic 82557 rev 08 and Real Tech NIC 8139 rev10
100on different slots (0-3) of the PCI and check:
101o Correct detection of the PCI devices.
102o Correct address mapping of the PCI devices.
1032)Insert Galileo 64120A rev 10 on different slots (0-3) of the PCI and check writing and reading pci configuration register through the U-Boot.
104
105Booting Linux through the U-Boot (use the bootargs of the U-Boot as a bootcmd to the kernal)