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git01.mediatek.com / filogic / uboot / fb9a73030dc65e449f3caccce9e16a80a7a94e08 / . / board / siemens / CCM / fpga_ccm.c
blob: 50b08abce7dece1e243481f2e556d33d51062f0e [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <common.h>
26#include <mpc8xx.h>
27#include <commproc.h>
28#include <common.h>
29
30#include "../common/fpga.h"
31
32fpga_t fpga_list[] = {
33 { "PUMA" , PUMA_CONF_BASE ,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]34 CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE }
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]35};
36int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
37
38void can_driver_enable (void);
39void can_driver_disable (void);
40
41#define _NOT_USED_ 0xFFFFFFFF
42
43/*
44 * PUMA access using UPM B
45 */
46const uint puma_table[] =
47{
48 /*
49 * Single Read. (Offset 0 in UPM RAM)
50 */
51 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
52 _NOT_USED_,
53 /*
54 * Precharge and MRS
55 */
56 _NOT_USED_, _NOT_USED_, _NOT_USED_,
57 /*
58 * Burst Read. (Offset 8 in UPM RAM)
59 */
60 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
62 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 /*
65 * Single Write. (Offset 18 in UPM RAM)
66 */
67 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
68 _NOT_USED_,
69 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70 /*
71 * Burst Write. (Offset 20 in UPM RAM)
72 */
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
77 /*
78 * Refresh (Offset 30 in UPM RAM)
79 */
80 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 /*
84 * Exception. (Offset 3c in UPM RAM)
85 */
86 0x7FFFFC07, /* last */
87 _NOT_USED_, _NOT_USED_, _NOT_USED_,
88};
89
90
91ulong fpga_control (fpga_t* fpga, int cmd)
92{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]93 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]94 volatile memctl8xx_t *memctl = &immr->im_memctl;
95
96 switch (cmd) {
97 case FPGA_INIT_IS_HIGH:
98 immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */
99 return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0;
100
101 case FPGA_INIT_SET_LOW:
102 immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
103 immr->im_ioport.iop_pcdat &= ~fpga->init_mask;
104 break;
105
106 case FPGA_INIT_SET_HIGH:
107 immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
108 immr->im_ioport.iop_pcdat |= fpga->init_mask;
109 break;
110
111 case FPGA_PROG_SET_LOW:
112 immr->im_ioport.iop_pcdat &= ~fpga->prog_mask;
113 break;
114
115 case FPGA_PROG_SET_HIGH:
116 immr->im_ioport.iop_pcdat |= fpga->prog_mask;
117 break;
118
119 case FPGA_DONE_IS_HIGH:
120 return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0;
121
122 case FPGA_READ_MODE:
123 /* disable FPGA in memory controller */
124 memctl->memc_br4 = 0;
125 memctl->memc_or4 = PUMA_CONF_OR_READ;
126 memctl->memc_br4 = PUMA_CONF_BR_READ;
127
128 /* (re-) enable CAN drivers */
129 can_driver_enable ();
130
131 break;
132
133 case FPGA_LOAD_MODE:
134 /* disable FPGA in memory controller */
135 memctl->memc_br4 = 0;
136 /*
137 * We must disable the CAN drivers first because
138 * they use UPM B, too.
139 */
140 can_driver_disable ();
141 /*
142 * Configure UPMB for FPGA
143 */
144 upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
145 memctl->memc_or4 = PUMA_CONF_OR_LOAD;
146 memctl->memc_br4 = PUMA_CONF_BR_LOAD;
147 break;
148
149 case FPGA_GET_ID:
150 return *(volatile ulong *)fpga->conf_base;
151
152 case FPGA_INIT_PORTS:
153 immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */
154 immr->im_ioport.iop_pcso &= ~fpga->init_mask;
155 immr->im_ioport.iop_pcdir &= ~fpga->init_mask;
156
157 immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */
158 immr->im_ioport.iop_pcso &= ~fpga->prog_mask;
159 immr->im_ioport.iop_pcdir |= fpga->prog_mask;
160
161 immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */
162 immr->im_ioport.iop_pcso &= ~fpga->done_mask;
163 immr->im_ioport.iop_pcdir &= ~fpga->done_mask;
164
165 break;
166
167 }
168 return 0;
169}