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git01.mediatek.com / filogic / uboot / fb97d318d4b9254d73c2e5f7a313e0993ee2c266 / . / configs / zynq_zc770_xm010_defconfig
blob: 2b8fb3c9214acf06dfe1efbfc849116333d7fa7b [file] [log] [blame]
Masahiro Yamadad5f8fee2015-03-12 13:24:39 +0900[diff] [blame]1CONFIG_ARM=y
Masahiro Yamada8204bd12015-03-16 16:43:24 +0900[diff] [blame]2CONFIG_ARCH_ZYNQ=y
Michal Simek92543872016-12-16 11:57:17 +0100[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x4000000
Michal Simekc7abf8d2017-12-01 13:50:33 +0100[diff] [blame]4CONFIG_SPL_STACK_R_ADDR=0x200000
Masahiro Yamada8c65b9d2014-09-22 19:59:06 +0900[diff] [blame]5CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
Michal Simek8691e812017-11-02 10:40:57 +0100[diff] [blame]6CONFIG_DEBUG_UART=y
Ruchika Guptae9a788d2015-01-23 16:01:53 +0530[diff] [blame]7CONFIG_FIT=y
Ruchika Guptae9a788d2015-01-23 16:01:53 +0530[diff] [blame]8CONFIG_FIT_SIGNATURE=y
Jagan Teki4c57e4c2017-01-21 11:48:33 +0100[diff] [blame]9CONFIG_FIT_VERBOSE=y
Lokesh Vutlafbad3702016-10-08 14:41:44 -0400[diff] [blame]10# CONFIG_DISPLAY_CPUINFO is not set
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]11CONFIG_SPL=y
Michal Simekc7abf8d2017-12-01 13:50:33 +0100[diff] [blame]12CONFIG_SPL_STACK_R=y
Heiko Schocher1d12ba22016-10-06 07:55:15 +0200[diff] [blame]13CONFIG_SPL_OS_BOOT=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]14CONFIG_HUSH_PARSER=y
Siva Durga Prasad Paladugu59d461e2016-01-11 12:01:10 +0530[diff] [blame]15CONFIG_SYS_PROMPT="Zynq> "
Michal Simek12e30a62017-11-02 10:38:16 +0100[diff] [blame]16CONFIG_CMD_BOOTZ=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]17# CONFIG_CMD_FLASH is not set
Simon Glass80cb1892017-05-17 03:25:21 -0600[diff] [blame]18CONFIG_CMD_FPGA_LOADBP=y
19CONFIG_CMD_FPGA_LOADFS=y
20CONFIG_CMD_FPGA_LOADMK=y
21CONFIG_CMD_FPGA_LOADP=y
Thomas Chou3a077cd2015-11-11 21:39:33 +0800[diff] [blame]22CONFIG_CMD_GPIO=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]23CONFIG_CMD_MMC=y
24CONFIG_CMD_SF=y
Joe Hershberger5a9d7f12015-06-22 16:15:30 -0500[diff] [blame]25# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]26CONFIG_CMD_TFTPPUT=y
27CONFIG_CMD_DHCP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]28CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]29CONFIG_CMD_PING=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]30CONFIG_CMD_CACHE=y
31CONFIG_CMD_EXT2=y
32CONFIG_CMD_EXT4=y
33CONFIG_CMD_EXT4_WRITE=y
34CONFIG_CMD_FAT=y
35CONFIG_CMD_FS_GENERIC=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]36CONFIG_ENV_IS_IN_SPI_FLASH=y
Masahiro Yamada88e2e362015-07-17 20:26:06 +0900[diff] [blame]37CONFIG_NET_RANDOM_ETHADDR=y
Nathan Rossidd71c8a2016-01-08 03:00:46 +1000[diff] [blame]38CONFIG_SPL_DM_SEQ_ALIAS=y
Michal Simek216f6372017-11-03 15:53:56 +0100[diff] [blame]39CONFIG_FPGA_XILINX=y
Masahiro Yamada7db8c172016-12-07 22:10:28 +0900[diff] [blame]40CONFIG_MMC_SDHCI=y
Michal Simek19abc1d2017-02-10 13:57:35 +0100[diff] [blame]41CONFIG_MMC_SDHCI_ZYNQ=y
Joe Hershberger17491a82015-06-22 16:15:29 -0500[diff] [blame]42CONFIG_SPI_FLASH=y
Michal Simekd4b2f102016-01-12 13:44:29 +0100[diff] [blame]43CONFIG_SPI_FLASH_BAR=y
Michal Simek27ebfbd2017-11-02 10:44:48 +0100[diff] [blame]44CONFIG_SPI_FLASH_MACRONIX=y
Bin Meng27f5b192015-11-25 05:34:54 -0800[diff] [blame]45CONFIG_SPI_FLASH_SPANSION=y
46CONFIG_SPI_FLASH_STMICRO=y
47CONFIG_SPI_FLASH_SST=y
48CONFIG_SPI_FLASH_WINBOND=y
Michal Simek3d7285f2015-11-30 14:34:52 +0100[diff] [blame]49CONFIG_ZYNQ_GEM=y
Michal Simek8691e812017-11-02 10:40:57 +0100[diff] [blame]50CONFIG_DEBUG_UART_ZYNQ=y
51CONFIG_DEBUG_UART_BASE=0xe0001000
52CONFIG_DEBUG_UART_CLOCK=50000000
Michal Simekab754532017-11-06 09:16:05 +0100[diff] [blame]53CONFIG_ZYNQ_SERIAL=y
Bin Meng72a049d2015-11-25 05:34:53 -0800[diff] [blame]54CONFIG_ZYNQ_SPI=y
Jagan Tekic6dca132015-08-31 17:38:40 +0530[diff] [blame]55CONFIG_ZYNQ_QSPI=y