Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 1 | /* |
Eric Bénard | 62d2b62 | 2010-08-09 11:50:45 +0200 | [diff] [blame] | 2 | * CPUAT91 by (C) Copyright 2006-2010 Eric Benard |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 3 | * eric@eukrea.com |
| 4 | * |
| 5 | * Configuration settings for the CPUAT91 board. |
| 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 8 | */ |
| 9 | |
Eric Bénard | 62d2b62 | 2010-08-09 11:50:45 +0200 | [diff] [blame] | 10 | #ifndef _CONFIG_CPUAT91_H |
| 11 | #define _CONFIG_CPUAT91_H |
Jens Scharsig | 128ecd0 | 2010-02-03 22:45:42 +0100 | [diff] [blame] | 12 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 13 | #include <asm/sizes.h> |
| 14 | |
| 15 | #ifdef CONFIG_RAMBOOT |
| 16 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 17 | #define CONFIG_SYS_TEXT_BASE 0x21F00000 |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 18 | #else |
| 19 | #define CONFIG_BOOTDELAY 1 |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 20 | #define CONFIG_SYS_TEXT_BASE 0 |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 21 | #endif |
| 22 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 23 | #define AT91C_XTAL_CLOCK 18432000 |
Andreas Bießmann | c2a1f0f | 2011-06-12 01:49:12 +0000 | [diff] [blame] | 24 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 25 | #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) |
| 26 | #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3) |
| 27 | #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) |
| 28 | #define CONFIG_SYS_HZ 1000 |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 29 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 30 | #define CONFIG_ARM920T |
| 31 | #define CONFIG_AT91RM9200 |
| 32 | #define CONFIG_CPUAT91 |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 33 | #define USE_920T_MMU |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 34 | |
Andreas Bießmann | c2a1f0f | 2011-06-12 01:49:12 +0000 | [diff] [blame] | 35 | #include <asm/hardware.h> /* needed for port definitions */ |
| 36 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 37 | #define CONFIG_CMDLINE_TAG |
| 38 | #define CONFIG_SETUP_MEMORY_TAGS |
| 39 | #define CONFIG_INITRD_TAG |
Andreas Bießmann | a631d2b | 2011-06-12 01:49:16 +0000 | [diff] [blame] | 40 | #define CONFIG_BOARD_EARLY_INIT_F |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 41 | |
| 42 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 43 | #define CONFIG_SYS_USE_MAIN_OSCILLATOR |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 44 | /* flash */ |
| 45 | #define CONFIG_SYS_MC_PUIA_VAL 0x00000000 |
| 46 | #define CONFIG_SYS_MC_PUP_VAL 0x00000000 |
| 47 | #define CONFIG_SYS_MC_PUER_VAL 0x00000000 |
| 48 | #define CONFIG_SYS_MC_ASR_VAL 0x00000000 |
| 49 | #define CONFIG_SYS_MC_AASR_VAL 0x00000000 |
| 50 | #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 |
| 51 | #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ |
| 52 | |
| 53 | /* clocks */ |
| 54 | #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ |
| 55 | #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */ |
| 56 | #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */ |
| 57 | |
| 58 | /* sdram */ |
| 59 | #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */ |
| 60 | #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 |
| 61 | #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 |
| 62 | #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ |
| 63 | #define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */ |
| 64 | #define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ |
| 65 | #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ |
| 66 | #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ |
| 67 | #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ |
| 68 | #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ |
| 69 | #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ |
| 70 | #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ |
| 71 | #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ |
| 72 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
| 73 | |
Andreas Bießmann | a631d2b | 2011-06-12 01:49:16 +0000 | [diff] [blame] | 74 | #define CONFIG_ATMEL_USART |
| 75 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 76 | #define CONFIG_USART_ID 0/* ignored in arm */ |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 77 | |
Eric Bénard | 62d2b62 | 2010-08-09 11:50:45 +0200 | [diff] [blame] | 78 | #undef CONFIG_HARD_I2C |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 79 | #undef CONFIG_SOFT_I2C |
Eric Bénard | 62d2b62 | 2010-08-09 11:50:45 +0200 | [diff] [blame] | 80 | #define AT91_PIN_SDA (1<<25) |
| 81 | #define AT91_PIN_SCL (1<<26) |
| 82 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 83 | #define CONFIG_SYS_I2C_INIT_BOARD |
Eric Bénard | 62d2b62 | 2010-08-09 11:50:45 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_I2C_SPEED 50000 |
| 85 | #define CONFIG_SYS_I2C_SLAVE 0 |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 86 | |
Eric Bénard | 62d2b62 | 2010-08-09 11:50:45 +0200 | [diff] [blame] | 87 | #define I2C_INIT i2c_init_board(); |
| 88 | #define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); |
| 89 | #define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); |
| 90 | #define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) |
| 91 | #define I2C_SDA(bit) \ |
| 92 | if (bit) \ |
| 93 | writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \ |
| 94 | else \ |
| 95 | writel(AT91_PMX_AA_TWD, &pio->pioa.codr); |
| 96 | #define I2C_SCL(bit) \ |
| 97 | if (bit) \ |
| 98 | writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \ |
| 99 | else \ |
| 100 | writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); |
| 101 | |
| 102 | #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) |
| 103 | |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 104 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 |
| 105 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 106 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 |
| 107 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 108 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 109 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 110 | #define CONFIG_BOOTP_BOOTPATH |
| 111 | #define CONFIG_BOOTP_GATEWAY |
| 112 | #define CONFIG_BOOTP_HOSTNAME |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 113 | |
| 114 | #include <config_cmd_default.h> |
| 115 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 116 | #define CONFIG_CMD_PING |
| 117 | #define CONFIG_CMD_MII |
| 118 | #define CONFIG_CMD_CACHE |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 119 | #undef CONFIG_CMD_USB |
| 120 | #undef CONFIG_CMD_FPGA |
| 121 | #undef CONFIG_CMD_IMI |
| 122 | #undef CONFIG_CMD_LOADS |
| 123 | #undef CONFIG_CMD_NFS |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 124 | #undef CONFIG_CMD_DHCP |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 125 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 126 | #ifdef CONFIG_SOFT_I2C |
| 127 | #define CONFIG_CMD_EEPROM |
| 128 | #define CONFIG_CMD_I2C |
| 129 | #endif |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 130 | |
| 131 | #define CONFIG_NR_DRAM_BANKS 1 |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 132 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 133 | #define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 134 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 135 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 136 | #define CONFIG_SYS_MEMTEST_END \ |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 137 | (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 138 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 139 | #define CONFIG_DRIVER_AT91EMAC |
| 140 | #define CONFIG_SYS_RX_ETH_BUFFER 16 |
| 141 | #define CONFIG_RMII |
| 142 | #define CONFIG_MII |
Eric Bénard | 58633c1 | 2010-06-21 09:40:43 +0200 | [diff] [blame] | 143 | #define CONFIG_DRIVER_AT91EMAC_PHYADDR 1 |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 144 | #define CONFIG_NET_RETRY_COUNT 20 |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 145 | #define CONFIG_KS8721_PHY |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 146 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 147 | #define CONFIG_SYS_FLASH_CFI |
| 148 | #define CONFIG_FLASH_CFI_DRIVER |
| 149 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 150 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 151 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 152 | #define CONFIG_SYS_FLASH_PROTECTION |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 153 | #define PHYS_FLASH_1 0x10000000 |
| 154 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 155 | #define CONFIG_SYS_MAX_FLASH_SECT 128 |
Eric Bénard | 62d2b62 | 2010-08-09 11:50:45 +0200 | [diff] [blame] | 156 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 157 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
| 158 | #define PHYS_FLASH_SIZE (16 * 1024 * 1024) |
| 159 | #define CONFIG_SYS_FLASH_BANKS_LIST \ |
| 160 | { PHYS_FLASH_1 } |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 161 | |
| 162 | #if defined(CONFIG_CMD_USB) |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 163 | #define CONFIG_USB_ATMEL |
| 164 | #define CONFIG_USB_OHCI_NEW |
| 165 | #define CONFIG_USB_STORAGE |
| 166 | #define CONFIG_DOS_PARTITION |
| 167 | #define CONFIG_AT91C_PQFP_UHPBU |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 168 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 169 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 170 | #define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE |
| 171 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" |
| 172 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
| 173 | #endif |
| 174 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 175 | #define CONFIG_ENV_IS_IN_FLASH |
| 176 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 128 * 1024) |
| 177 | #define CONFIG_ENV_SIZE (128 * 1024) |
| 178 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 179 | |
| 180 | #define CONFIG_SYS_LOAD_ADDR 0x21000000 |
| 181 | |
| 182 | #define CONFIG_BAUDRATE 115200 |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 183 | |
| 184 | #define CONFIG_SYS_PROMPT "CPUAT91=> " |
| 185 | #define CONFIG_SYS_CBSIZE 256 |
| 186 | #define CONFIG_SYS_MAXARGS 32 |
| 187 | #define CONFIG_SYS_PBSIZE \ |
| 188 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 189 | #define CONFIG_CMDLINE_EDITING |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 190 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 191 | #define CONFIG_SYS_MALLOC_LEN \ |
| 192 | ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024) |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 193 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 194 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ |
| 195 | GENERATED_GBL_DATA_SIZE) |
| 196 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 197 | #define CONFIG_DEVICE_NULLDEV |
| 198 | #define CONFIG_SILENT_CONSOLE |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 199 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 200 | #define CONFIG_AUTOBOOT_KEYED |
Eric Benard | 1479026 | 2009-10-12 10:15:39 +0200 | [diff] [blame] | 201 | #define CONFIG_AUTOBOOT_PROMPT \ |
| 202 | "Press SPACE to abort autoboot\n" |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 203 | #define CONFIG_AUTOBOOT_STOP_STR " " |
| 204 | #define CONFIG_AUTOBOOT_DELAY_STR "d" |
| 205 | |
Eric Benard | c2e1f23 | 2011-04-03 06:35:55 +0000 | [diff] [blame] | 206 | #define CONFIG_VERSION_VARIABLE |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 207 | |
| 208 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0" |
| 209 | #define MTDPARTS_DEFAULT \ |
| 210 | "mtdparts=physmap-flash.0:" \ |
| 211 | "128k(u-boot)ro," \ |
| 212 | "128k(u-boot-env)," \ |
Eric Bénard | 56a5fb0 | 2010-08-09 11:50:46 +0200 | [diff] [blame] | 213 | "1792k(kernel)," \ |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 214 | "-(rootfs)" |
| 215 | |
| 216 | #define CONFIG_BOOTARGS \ |
| 217 | "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200" |
| 218 | |
| 219 | #define CONFIG_BOOTCOMMAND "run flashboot" |
| 220 | |
| 221 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 222 | "mtdid=" MTDIDS_DEFAULT "\0" \ |
| 223 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ |
| 224 | "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \ |
| 225 | "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \ |
| 226 | "10000000 ${filesize}\0" \ |
| 227 | "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \ |
Eric Bénard | 56a5fb0 | 2010-08-09 11:50:46 +0200 | [diff] [blame] | 228 | "1019ffff; erase 10040000 101fffff; cp.b 21000000 " \ |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 229 | "10040000 ${filesize}\0" \ |
| 230 | "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \ |
Eric Bénard | 56a5fb0 | 2010-08-09 11:50:46 +0200 | [diff] [blame] | 231 | "10200000 10ffffff; erase 10200000 10ffffff; cp.b " \ |
| 232 | "21000000 10200000 ${filesize}\0" \ |
Tom Rix | 3db7af7 | 2009-09-27 07:47:24 -0500 | [diff] [blame] | 233 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ |
| 234 | "flashboot=run ramargs;bootm 10040000\0" \ |
| 235 | "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \ |
| 236 | "bootm 21000000\0" |
Eric Bénard | 62d2b62 | 2010-08-09 11:50:45 +0200 | [diff] [blame] | 237 | #endif /* _CONFIG_CPUAT91_H */ |